Ultra-thin Body Buried In<sub>0.35</sub>Ga<sub>0.65</sub>As Channel MOSFETs with Extremely Low Off-current on Si Substrates

WANG Bo; DING Peng; FENG Ruize; WANG Yanfu; LIU Xiaoyu; SUN Tangyou; CHEN Yonghe; LIU Xingpeng; LI Qi; LI Yue; LIU Yingbo; YIN Yihui; ZHAO Hao; ZHANG Wei; LI Haiou; JIN Zhi

doi:10.1049/cje.2021.07.024

Volume 30 Issue 6

Nov. 2021

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Article Navigation > Chinese Journal of Electronics > 2021 > 30(6): 1017-1021

WANG Bo, DING Peng, FENG Ruize, et al., “Ultra-thin Body Buried In0.35Ga0.65As Channel MOSFETs with Extremely Low Off-current on Si Substrates,” Chinese Journal of Electronics, vol. 30, no. 6, pp. 1017-1021, 2021, doi: 10.1049/cje.2021.07.024

Citation:

WANG Bo, DING Peng, FENG Ruize, et al., “Ultra-thin Body Buried In_0.35Ga_0.65As Channel MOSFETs with Extremely Low Off-current on Si Substrates,” Chinese Journal of Electronics, vol. 30, no. 6, pp. 1017-1021, 2021, doi: 10.1049/cje.2021.07.024

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Ultra-thin Body Buried In_0.35Ga_0.65As Channel MOSFETs with Extremely Low Off-current on Si Substrates

doi: 10.1049/cje.2021.07.024

1. Guangxi Key Laboratory of Precision Navigation Technology and Application, Guilin University of Electronic Technology, Guilin 541004, China;
2. High-Frequency High-Voltage Device and Integrated Circuits Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;
3. The 34th Research Institute of China Electronics Technology Group Corporation, Guilin 541004, China;
4. State Key Laboratory of ASIC & System, Fudan University, Shanghai 200433, China

Funds:

This work is supported by the National Natural Science Foundation of China (No.61874036, No.61805053), the Open Project of State Key Laboratory of ASIC and System (No.KVH1233021), the Guangxi Innovation Research Team Project (No.2018GXNSFGA281004, No.2018GXNSFBA281152), the Guangxi Innovation Driven Development Special Fund Project (No.AA19254015), and the Guangxi Key Laboratory of Precision Navigation Technology and Application Project (No.DH202020, No.DH202001).

Received Date: 2020-10-28
Rev Recd Date: 2021-01-11

Available Online: 2021-09-23

Publish Date: 2021-11-05

Abstract

Abstract

In this paper, we investigated the electrical properties of the Metal-oxide-semiconductor gate stack of Ti/Al₂O₃/InP under different annealing conditions. A minimum interface trap density of 3×10¹¹cm^-2eV^-1 is obtained without postmetallization annealing treatment. Additionally, utilizing Ti/Al₂O₃/InP MOS gate stack, we fabricated ultra-thin body buried In_0.35Ga_0.65As channel MOSFETs on Si substrates with optimized on/off trade-off. The 200nm gate length device with extremely low off-current of 0.6nA/µm, and on-off ratio of 3.3×10⁵, is demonstrated by employing buried low indium (In_0.35Ga_0.65As) channel with InP barrier/spacer device structure, giving strong potential for future highperformance and low-power applications.
- Buried low indium channel,
- Si substrate,
- Wafer bonding,
- Off-current

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References(17)

References

Y.Q. Wu, W.K. Wang, O. Koybasi, et al., "0.8-V supply voltage deep-submicrometer inversion-mode In_0.75Ga_0.25As MOSFET", IEEE Electron Device Lett, Vol.30, No.7, pp.700-702, 2009.

M. Egard, L. Ohlsson, B.M. Borg, et al., "High transconductance self-aligned gate-last surface channel In_0.53Ga_0.47As MOSFET", International Electron Devices Meeting (IEDM), Washington, DC, USA, pp.303-306, 2011.

C.Y. Chang, C. Yokoyama, M. Takenaka, et al., "Impact of La₂O₃/InGaAs MOS interfaces on the performance of InGaAs MOSFETs", IEEE Trans. Electron Devices, Vol.64, No.6, pp.2519-2525, 2017.

S.K. Wang, B. Sun, M.M. Cao, et al., "Modification of Al₂O₃/InP interfaces using sulfur and nitrogen passivations", Journal of Applied Physics, Vol.121, pp.184104, 2017.

S. Son, J.H. Park, J. Baek, et al., "Record effective mobility obtained from In_0.53Ga_0.47As/In_0.52Ga_0.48As quantum-well MOSFETs on 300-mm Si substrate", IEEE Electron Device Lett, Vol.38, No.6, pp.724-727, 2017.

M.L. Huang, S.W. Chang, M.K. Chen, et al., "In_0.53Ga_0.47As MOSFETs with high channel mobility and gate stack quality fabricated on 300 mm Si substrate", Symposium on VLSI Technology (VLSI Technology), Kyoto, Japan, pp.T204-T205, 2015.

N. Waldron, C. Merckling, W. Guo, et al., "An InGaAs/InP quantum well FinFet using the replacement Fin process integrated in an RMG flow on 300mm Si substrates", Symposium on VLSI Technology (VLSI-Technology), Honolulu, HI, USA, pp.1-2, 2014.

L. Czornomaz, E. Uccelli, M. Sousa, et al., "Confined epitaxial lateral overgrowth (CELO):A novel concept for scalable integration of CMOS-compatible InGaAs-oninsulator MOSFETs on large-area Si substrates", Symposium on VLSI Technology (VLSI Technology), Kyoto, Japan, pp.T172-173, 2015.

S.K. Kim, J. Shim, D.M. Geum, et al., "Impact of ground plane doping and bottom-gate biasing on electrical properties in In_0.53Ga_0.47As-OI MOSFETs and donor wafer reusability toward monolithic 3-D integration with In_0.53Ga_0.47As channel", IEEE Trans. Electron Devices, Vol.65, No.5, pp.1862-1868, 2018.

S.K. Kim, J. Shim, D.M. Geum, et al., "Cost-effective fabrication of In_0.53Ga_0.47As-on-insulator on Si for monolithic 3D via novel epitaxial lift-off (ELO) and donor wafer re-use", IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp.616-619, 2016.

S.K. Kim, J. Shim, D.M. Geum, et al., "Fabrication of InGaAs-on-insulator substrates using direct wafer-bonding and epitaxial lift-off techniques", IEEE Trans. Electron Devices, Vol.64, No.9, pp.3601-3608, 2017.

J. Lin, L. Czornomaz, N. Daix, et al., "Ultrathin body InGaAs MOSFETs on III-V-on-insulator integrated with Silicon active substrate (III-V-OIAS)", IEEE Trans. Electron Devices, Vol.63, No.8, pp.3088-3095, 2016.

S.H. Kim, D.M. Geum, M.S. Park, et al., "In_0.53Ga_0.47 Ason-insulator metal-oxide-semiconductor field-effect transistors utilizing Y2O3 buried oxide", IEEE Electron Device Lett, Vol.36, No.5, pp.451-453, 2015.

J.Q. Lin, L. Czornomaz, N. Daix et al., "Ultra-thin-body selfaligned InGaAs MOSFETs on insulator (III-V-O-I) by a tightpitch process", Device Research Conference, Santa Barbara, CA, USA, pp.217-218, 2014.

L. Czornomaz, N. Daix, P. Kerber, et al., "Scalability of ultra-thin-body and BOX InGaAs MOSFETs on silicon", Proceedings of the European Solid-State Device Research Conference (ESSDERC), Bucharest, Romania, pp.143-146, 2013.

C.B. Zota, C. Convertino, M. Sousa, et al., "Highfrequency quantum well InGaAs-on-Si MOSFETs with scaled gate lengths", IEEE Electron Device Lett, Vol.40, No.4, pp.538-541, 2019.

R. Castagne and A. Vapaille, "Apparent interface state density introduced by the spatial fluctuations of surface potential in an m.o.s. structure", Electron. Lett., Vol.6, No.22, pp.691-694, 1970.

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