Optimized Mid-bond Order for 3D-Stacked ICs Considering Failed Bonding

LIANG Huaguo; CHANG Hao; LI Yang; WANG Wei; CHEN Tian; XU Hui

doi:10.1049/cje.2015.04.001

Volume 24 Issue 2

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Article Navigation > Chinese Journal of Electronics > 2015 > 24(2): 223-228

LIANG Huaguo, CHANG Hao, LI Yang, et al., “Optimized Mid-bond Order for 3D-Stacked ICs Considering Failed Bonding,” Chinese Journal of Electronics, vol. 24, no. 2, pp. 223-228, 2015, doi: 10.1049/cje.2015.04.001

Citation:

LIANG Huaguo, CHANG Hao, LI Yang, et al., “Optimized Mid-bond Order for 3D-Stacked ICs Considering Failed Bonding,” Chinese Journal of Electronics, vol. 24, no. 2, pp. 223-228, 2015, doi: 10.1049/cje.2015.04.001

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Optimized Mid-bond Order for 3D-Stacked ICs Considering Failed Bonding

doi: 10.1049/cje.2015.04.001

1.
School of Electronic Science & Applied Physics, Hefei University of Technology, Hefei 230009, China;
2.
School of Computer and Information, Hefei University of Technology, Hefei 230009, China;
3.
Department of Computer Science & Technology, Anhui University of Finance & Economics, Bengbu 233030, China

Funds: This work is supported by the National Nature Science Foundation of China (No.61274036, No.61371025, No.61306046, No.61204046, No.61106038, No.61106037), and Doctoral Fund of Ministry of Education of China (No.20110111120012).

More Information

Corresponding author: CHANG Hao was born in 1983. He is now pursuing Ph.D. degree in School of Computer and Information, Hefei University of Technology. His research interests include 3DSICs integration and test, built-in selftest and fault tolerance. (Email:007changhao@163.com)
Publish Date: 2015-04-10

Abstract

Abstract

One notable difference between 3D test flow and 2D test flow mainly lies in the mid-bond test, in which the stacking yield can be further enhanced through optimized bonding arrangement. In contrast to the existing sequential stacking, this paper proposes a novel rearranged stacking scheme which estimates the probability and cost of failed bonding in each stacking step and optimizes the mid-bond order to screen out the failed component as early as possible. The effect of the rearranged stacking has been extensively analyzed using the yield model and cost model of 3D-SICs considering different process parameters such as die yield, stacking size, failure rate and redundancy degree of TSVs. Experimental results demonstrate that the proposed rearranged stacking method is only a half of the sequential stacking in terms of Failed area ratio (FAR).
- 3D-Stacked ICs,
- Through silicon via (TSV),
- 3D-SICs test,
- Sequential stacking,
- Rearranged stacking,
- Abort on fail

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References(20)

References

P. Garrou, C. Bower and P. Ramm, Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits, Vol.1-2, Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim, Germany, 2008.

H. Lee and K. Chakrabarty, “Test challenges for 3D integrated circuits”, IEEE Design & Test of Computers, Vol.26, No.5, pp.26-35, 2009.

L.R. Huang, S.Y. Huang, S. Sunter, et al., “Oscillationbased prebond TSV test”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.32, No.9, pp.1440-1444, 2013.

S. Kele and X. Dong, “Three dimensional ICs thermal-driven test application scheme”, Acta Electronica Sinica, Vol.41, No.6, pp.1202-1206, 2013.(in Chinese)

Y.J. Huang, J.F. Li, J.J. Chen, et al., “A built-in self-test scheme for the post-bond test of TSVs in 3D ICs”, Proc. of IEEE 29th VLSI Test Symposium, Dana Point, California, USA, pp.20-25, 2011.

B. Noia, K. Chakrabarty, S.K. Goel, et al., “Test architecture optimization and test scheduling for TSV-Based 3-D stacked ICs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.30, No.11, pp.1705-1718, 2011.

E.J. Marinissen, “Testing TSV-based three-dimensional stacked ICs”, Proc. of Design, Automation & Test in Europe Conference & Exhibition, Dresden, Germany, pp.1689-1694, 2010.

M. Taouil and S. Hamdioui, “Stacking order impact on overall 3D die-to-wafer stacked-IC cost”, Proc. of IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, Cottbus, Germany, pp.335-340, 2011.

U. Ingelsson, S.K. Goel, E. Larsson, et al., “Test scheduling for modular SOCs in an abort-on-fail environment”, Proc. of European Test Symposium, Tallinn, Estonia, pp.8-13, 2005.

P. Mercier, S.R. Singh, K. Iniewski, et al., “Yield and cost modeling for 3D chip stack technologies”, Proc. of IEEE Custom Integrated Circuits Conference, pp.357-360, 2006.

X. Qiang, J. Li, L. Huiyun, et al., “Yield enhancement for 3Dstacked ICs: Recent advances and challenges”, Proc. of 17th Asia and South Pacific Design Automation Conference, Sydney, Australia, pp.731-737, 2012.

C. Yibo, N. Dimin and X. Yuan, “Cost-effective integration of Three-dimensional (3D) ICs emphasizing testing cost analysis”, IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, USA, pp.471-476, 2010.

L. Jiang, F. Ye, Q. Xu, et al., “On effective and efficient in-field TSV repair for stacked 3D ICs”, Proc. of 50th ACM/IEEE Design Automation Conference, Austin, USA, pp.1-6, 2013.

M. Taouil, S. Hamdioui, K. Beenakker, et al., “Test impact on the overall die-to-Wafer 3D stacked IC cost”, Journal of Electronic Testing-Theory and Applications, Vol.28, No.1, pp.15-25, 2012.

D. Xiangyu, Z. Jishen and X. Yuan, “Fabrication cost analysis and cost-aware design space exploration for 3-D ICs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.29, No.12, pp.1959-1972, 2010.

X. Wu, G. Sun, X. Dong, et al., “Cost-driven 3D integration with interconnect layers”, Proc. of 47th ACM/IEEE Design Automation Conference (DAC), Anaheim, USA, pp.150-155, 2010.

D.H. Kim, K. Athikulwongse, M. Healy, et al., “3D-MAPS: 3D massively parallel processor with stacked memory”, Proc. of IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, pp.188-190, 2012.

D.H. Kim, S. Mukhopadhyay and S.K. Lim, “Through-siliconvia aware interconnect prediction and optimization for 3D stacked ICs”, Proc. of the 11th International Workshop on System Level Interconnect Prediction, San Francisco, CA, USA, pp.85-92, 2009.

K.P. Parker, “3D-IC defect investigation”, available at http://grouper.ieee.org/groups/3Dtest/statusReports/TigerTeamDefectInvestigation20120705. pdf, 2012-7.

A.C. Hsieh and T.T. Hwang, “TSV redundancy: Architecture and design issues in 3-D IC”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.20, No.4, pp.711-722, 2012.

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