YANG Liqun, YANG Haigang, LI Wei, et al., “Efficiently Exploring FPGA Design Space Based on Semi-Supervised Learning,” Chinese Journal of Electronics, vol. 25, no. 1, pp. 58-63, 2016, doi: 10.1049/cje.2016.01.009
Citation: YANG Liqun, YANG Haigang, LI Wei, et al., “Efficiently Exploring FPGA Design Space Based on Semi-Supervised Learning,” Chinese Journal of Electronics, vol. 25, no. 1, pp. 58-63, 2016, doi: 10.1049/cje.2016.01.009

Efficiently Exploring FPGA Design Space Based on Semi-Supervised Learning

doi: 10.1049/cje.2016.01.009
Funds:  This work is supported by National Natural Science Foundation of China (No.61271149) and National Science and Technology Major Project of China (No.2013ZX03006004).
More Information
  • Corresponding author: YANG Haigang (corresponding author) received B.Sc. and M.Sc. degrees from Fudan University, China in 1983 and 1986, respectively, and the Ph.D. degree from University of Cambridge, United Kingdom in 1991. He had previously been working with Wolfson Micro-electronics, LSI Logic Europe, Hitachi Microsystems Europe and Altera Europe. He currently works with Institute of Electronics, Chinese Academy of Sciences, as professor and director of the Systemon- Programmable Chip Research Department. His main research interests include analog and mixed signal integrated circuit design, VLSI design, etc. (Email: yanghg@mail.ie.ac.cn)
  • Received Date: 2014-01-27
  • Rev Recd Date: 2014-06-30
  • Publish Date: 2016-01-10
  • Design space exploration (DSE) is an important step before the physical level design of Field programmable gate arrays (FPGA). An optimum architecture is usually selected from the whole space. As the architecture parameters increase, the huge time cost to explore an exponentially increasing space makes this method unrealistic. We propose a novel predictive modeling approach called ECOMT to estimate the area and delay of a circuit which is mapped onto an FPGA with certain architecture. Semi-supervised model tree is adopted to model the performance with respect to architecture parameters. Combined with nonlinear programming, the area and delay model obtained can be used to guide the DSE. Experimental results show that the model trained through ECOMT has Mean relative error (MRE) below 5% compared to VTR. Meanwhile the time used to attain the model is less than 3 minutes, which reduces the time of DSE considerably.
  • loading
  • V. Betz, J. Rose and A. Marquardt, Architecture and CAD for Deep-submicron FPGAs, Kluwer Academic Publishers, 1999.
    A. Marquardt, V. Betz and J. Rose, “Speed and area tradeoffs in cluster-based FPGA architectures”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.8, No.1, pp.84-93, 2000.
    E. Ahmed and J. Rose, “The effect of LUT and cluster size on deep-submicron FPGA performance and density”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.12, No.3, pp.288-298, 2004.
    F. Li, Y. Lin, L. He, et al., “Power modeling and characteristics of field programmable gate arrays”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.24, No.11, pp.1712-1724, 2005.
    J. Rose, J. Luu, C. W. Yu, et al., “The VTR project: Architecture and CAD for FPGAs from verilog to routing”, ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, USA, pp.77-86, 2012.
    H. Gao, Y. Yang, X. Ma, et al., “Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations”, 6th International Symposium on Quality of Electronic Design, IEEE Computer Society, San Jose, USA, pp.370-374, 2005.
    A.M. Smith, S.J.E. Wilton and J. Das, “Wirelength modeling for homogeneous and heterogeneous FPGA architectural development”, ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, USA, pp.181-190, 2009.
    J. Das, A. Lam, S.J.E. Wilton, et al., “An analytical model relating FPGA architecture to logic density and depth”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.19, No.12, pp.2229-2242, 2011.
    J. Das and S.J.E. Wilton, “An analytical model relating FPGA architecture parameters to routability”, 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, USA, pp.181-184, 2011.
    E. Ipek, S.A. McKee, R. Caruana, et al., “Efficiently exploring architectural design spaces via predictive modeling”, 12th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, USA, pp.195-206, 2006.
    Q. Guo, T. Chen, Y. Chen, et al., “Effective and efficient microprocessor design space exploration using unlabeled design configurations”, International Joint Conference on Artificial Intelligence (IJCAI), Vol.22, No.1, pp.1671-1677, 2011.
    Q. Guo, T. Chen, Y. Chen, et al., “Microarchitectural design space exploration made fast”, Microprocessors and Microsystems, Vol.37, No.1, pp.41-51, 2013.
    Z. Zhou and M. Li, “Semi-supervised regression with cotraining”, International Joint Conference on Artificial Intelligence (IJCAI), Edinburgh, UK, pp.908-916, 2005.
    P.J. Joseph, K. Vaswani and M.J. Thazhuthaveetil, “Construction and use of linear regression models for processor performance analysis”, The Twelfth International Symposium on High-Performance Computer Architecture, Austin, USA, pp.99-108, 2006.
    Q. Liu, J. Ma and Q. Zhang, “Neural network based preplacement wirelength estimation”, The International Conference on Field-Programmable Technology, Seoul, Korea, pp.16- 22, 2012.
    Y. Wang and I.H. Witten, “Induction of model trees for predicting continuous classes”, 9th European Conference on Machine Learning, Prague, Czech Republic, 1997.
    A.M. Smith, G.A. Constantinides and P.Y.K. Cheung, “FPGA architecture optimization using geometric programming”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.29, No.8, pp.1163-1176, 2010.
    D. Xie, J. Lai and J. Tong, “Research of efficient utilization routing algorithm for current FPGA”, Chinese Journal of Electronics, Vol.19, No.1, pp.48-52, 2010.
  • 加载中

Catalog

    通讯作者: 陈斌, bchen63@163.com
    • 1. 

      沈阳化工大学材料科学与工程学院 沈阳 110142

    1. 本站搜索
    2. 百度学术搜索
    3. 万方数据库搜索
    4. CNKI搜索

    Article Metrics

    Article views (469) PDF downloads(503) Cited by()
    Proportional views
    Related

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return