A Reconfigurable Hardware Architecture for Packet Processing

DUAN Tong; LAN Julong; HU Yuxiang; LIU Shiran

doi:10.1049/cje.2017.08.018

Volume 27 Issue 2

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DUAN Tong, LAN Julong, HU Yuxiang, et al., “A Reconfigurable Hardware Architecture for Packet Processing,” Chinese Journal of Electronics, vol. 27, no. 2, pp. 428-432, 2018, doi: 10.1049/cje.2017.08.018

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DUAN Tong, LAN Julong, HU Yuxiang, et al., “A Reconfigurable Hardware Architecture for Packet Processing,” Chinese Journal of Electronics, vol. 27, no. 2, pp. 428-432, 2018, doi: 10.1049/cje.2017.08.018

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A Reconfigurable Hardware Architecture for Packet Processing

doi: 10.1049/cje.2017.08.018

National Digital Switching System & Engineering Technological Research Center, Zhengzhou 450002, China

Funds: This work is supported by the National Basic Research Program of China (973) (No.2012CB315901, No.2013CB329104), the National Natural Science Foundation of China (No.61521003, No.61372121, No.61309019), and the National High Technology Research and Development Program of China (863) (No.2013AA013505, No.2015AA016102).

Received Date: 2015-12-04
Rev Recd Date: 2016-05-31
Publish Date: 2018-03-10

Abstract

Abstract

In this paper, we propose a reconfigurable packet processing hardware architecture for future switch, in which several protocol-independent action units are introduced to remove the protocol dependence of conventional packet processors. With the proposed architecture, any specified header fields can be mapped into the right action unit, so that the processor can meet any packet processing demands. To reduce the hardware resource cost, the processor cost model and optimization algorithm are proposed. The NetFPGA-based implementation shows a throughput of 94Gb/s with 64-B packets. The programmability cost is approximately 1.5 times of conventional design, which consumes only 8% of the total FPGA resources.
- Packet processing,
- Hardware architecture,
- Reconfigurable,
- Protocol-independent

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References(16)

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