A Self-Biased Low-Jitter Process-Insensitive Phase-Locked Loop for 1.25 Gb/s-6.25Gb/s SerDes

YUAN Hengzhou; GUO Yang; LIU Yao; LIANG Bin; GUO Qiancheng

doi:10.1049/cje.2018.02.003

Volume 27 Issue 5

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Article Navigation > Chinese Journal of Electronics > 2018 > 27(5): 1009-1014

YUAN Hengzhou, GUO Yang, LIU Yao, et al., “A Self-Biased Low-Jitter Process-Insensitive Phase-Locked Loop for 1.25 Gb/s-6.25Gb/s SerDes,” Chinese Journal of Electronics, vol. 27, no. 5, pp. 1009-1014, 2018, doi: 10.1049/cje.2018.02.003

Citation:

YUAN Hengzhou, GUO Yang, LIU Yao, et al., “A Self-Biased Low-Jitter Process-Insensitive Phase-Locked Loop for 1.25 Gb/s-6.25Gb/s SerDes,” Chinese Journal of Electronics, vol. 27, no. 5, pp. 1009-1014, 2018, doi: 10.1049/cje.2018.02.003

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A Self-Biased Low-Jitter Process-Insensitive Phase-Locked Loop for 1.25 Gb/s-6.25Gb/s SerDes

doi: 10.1049/cje.2018.02.003

College of Computer Science, National University of Defense Technology, Changsha 410073, China

Funds: This work is supported by the National Natural Science Foundation of China (No.61772540).

More Information

Corresponding author: GUO Yang (corresponding author) was born in Zhejiang. He received the Ph.D. degree in Microelectronics and Solid State Electronics from National University of Defence Technology, China. He is a professor of National University of Defence Technology. His research interests include high speed analog circuits and electronic design automation algorithm. (Email:guoyang@nudt.edu.cn)
Received Date: 2016-02-26
Rev Recd Date: 2016-08-17
Publish Date: 2018-09-10

Abstract

Abstract

The paper presents a fully integrated multiphase output low-jitter CMOS phase-locked loop for 1.25Gb/s to 6.25Gb/s wireline SerDes transmitter clocking. The self-biased bandwidth technology with simplified structure is applied to reduce the sensitivity to process variations. A differential Charge pump (CP) which is suitable for low power supply and process migration is proposed. An accelerator is built to avoid the disadvantage of great damping factor. Self-adaptive frequency dividers are used to improve power efficiency. The simulation results under 65nm and 55nm process almost maintain almost the same jitter performance and show the high process insensitivity and good jitter performance.
- Phase-locked loop (PLL),
- Self-biased,
- Low-jitter,
- Process-insensitive,
- Serializer-deserializer

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References(14)

References

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