A CDR System Based on Improved Second Order Digital Filter, Hysteretic Voter and Phase Interpolator

ZHAO Yuyue; JIANG Yingdan; YANG Yu; SHEN Guangzhen; HU kai; YAN Hua

doi:10.1049/cje.2019.08.006

Volume 28 Issue 6

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Article Navigation > Chinese Journal of Electronics > 2019 > 28(6): 1227-1233

ZHAO Yuyue, JIANG Yingdan, YANG Yu, et al., “A CDR System Based on Improved Second Order Digital Filter, Hysteretic Voter and Phase Interpolator,” Chinese Journal of Electronics, vol. 28, no. 6, pp. 1227-1233, 2019, doi: 10.1049/cje.2019.08.006

Citation:

ZHAO Yuyue, JIANG Yingdan, YANG Yu, et al., “A CDR System Based on Improved Second Order Digital Filter, Hysteretic Voter and Phase Interpolator,” Chinese Journal of Electronics, vol. 28, no. 6, pp. 1227-1233, 2019, doi: 10.1049/cje.2019.08.006

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A CDR System Based on Improved Second Order Digital Filter, Hysteretic Voter and Phase Interpolator

doi: 10.1049/cje.2019.08.006

1.
East Technologies Incorporated, Wuxi 214072, China;
2.
China Electronics Technology Group Corporation No. 58 Research Institute, Wuxi 214072, China

Received Date: 2017-07-26
Rev Recd Date: 2018-10-12
Publish Date: 2019-11-10

Abstract

Abstract

The proposed Clock and data recovery system (CDRS) has three improved parts. The second order digital filter with rounding algorithm implements fractional gain and avoids direct current quantization noise which varies between -q/2 and +q/2 while that of traditional filter varies between 0 and +q (q is quantization step). The hysteresis majority voter can combat high frequency and strong jitter especially in quasi-steady state. The improved Phase interpolator (PI) has much smaller current-switching glitch and phase glitch since the weighting current changes gradually instead of steeply. The optimized CDRS can handle up to±6000ppm (parts per million) frequency offset and the phase resolution is 1.4o/LSB (Least significant bit) according to analysis. The simulations of jitter transfer function and jitter tolerance by Matlab, simulations of phase noise by spectre using Verilog+VeriloA model, and measurements of frequency offset and jitter tolerance all show its good performance.
- CDRS,
- Bang-bang phase detector(!!PD),
- Hysteretic voter,
- Second order digital filter,
- Phase interpolator,
- Jitter transfer,
- Jitter tolerance

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References(10)

References

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