Volume 31 Issue 1
Jan.  2022
Turn off MathJax
Article Contents
WANG Tonghui, ZOU Jiaxuan, QI Huanhuan, et al., “A Programmable Pre-emphasis Technique with Combined RLC Source Degeneration for High-Speed Serial Link Transmitters,” Chinese Journal of Electronics, vol. 31, no. 1, pp. 52-58, 2022, doi: 10.1049/cje.2021.00.055
Citation: WANG Tonghui, ZOU Jiaxuan, QI Huanhuan, et al., “A Programmable Pre-emphasis Technique with Combined RLC Source Degeneration for High-Speed Serial Link Transmitters,” Chinese Journal of Electronics, vol. 31, no. 1, pp. 52-58, 2022, doi: 10.1049/cje.2021.00.055

A Programmable Pre-emphasis Technique with Combined RLC Source Degeneration for High-Speed Serial Link Transmitters

doi: 10.1049/cje.2021.00.055
Funds:  This work was supported by the National Natural Science Foundation of China (61974118, 62004156)
More Information
  • Author Bio:

    received the B.S. degree in microelectronics science and engineering from Xi’an Jiaotong University (XJTU), Xi’an, China, in 2019. He is currently pursing the M.S. degree in electronic science and technology from Xi’an Jiaotong University. His research interests include analog interface and high-speed SerDes circuit design. (Email: wang578503930@stu.xjtu.edu.cn)

    received the B.S. degree in materials science and engineering from Huazhong University of Science and Technology, Wuhan, China, in 2005, and M.S. degree in communication and information systems from Guilin University of Electronic Technology, Guilin, China, in 2009. He is working toward the Ph.D. degree in microelectronics from Xidian University, Xi’an, China. Since 2009, he has been with China Electronic Technology Group Corporation, No.58 Research Institute, Wuxi, China, where he is involved in CMOS analog and mixed mode integrated circuit design, especially Clock and PLL

    received the B.S. degree in electronic science and technology and the M.S. degree in microelectronics and solid-state electronics from Xi’an Jiaotong University, Xi’an, China, in 2005 and 2008 respectively. From 2008 to 2018, she focused on high speed analog and mixed-signal CMOS circuits such as frequency synthesizers and data transceivers. Since 2018, she has been working as an Engineer in Xi’an Jiaotong University, where she is pursing the Ph.D. degree in microelectronics

    received the B.S. degree in microelectronics science and engineering from Xi’an Jiaotong University, Xi’an, China, in 2019. He is currently pursing the M.S. degree in electronic science and technology from Xi’an Jiaotong University, Xi’an, China. His research interests include analog interface and PLL circuit design

    received the B.S. degree in electronic information engineering from Northwest A&F University, Xianyang, China, in 2018. He is currently pursing the M.S. degree in integrated circuit engineering from Xi’an Jiaotong University, Xi’an, China. His research interests include analog interface and high-speed SerDes circuit design

    (corresponding author) received the B.S. degree in electronic engineering from the Xi’an University of Technology in 2000 and the Ph.D. degree in electronic engineering from XJTU, in 2008. Since 2008, he has been with the Department of Microelectronics, XJTU, where he is currently a Professor. From June 2009 to Sept. 2009, he was a Visiting Scholar at KU Leuven and IMEC, Belgium. From 2016 to 2017, he was a Visiting Professor with the Department of the Electrical and Computer Engineering, University of Toronto. His research interests include analog/mixed-signal IC design, such as ADC, low-power and low-voltage references, and bio-medical ICs. (Email: hongzhang@xjtu.edu.cn)

  • Received Date: 2021-02-02
  • Accepted Date: 2021-05-10
  • Available Online: 2021-10-08
  • Publish Date: 2022-01-05
  • This paper presents a clock-less programmable pre-emphasis technique realized by a driver with combined resistive-inductive-capacitive source degeneration for high-speed serial link transmitters. The addition of a series inductive-capacitive resonance network expands the bandwidth of the driver without lowering down the pre-emphasis gain. The driver with the proposed pre-emphasis technique provides adjustable gain from mid-frequency to high-frequency which is controlled by a tunable tail current, offering the capability for the transmitter to adapt to different cable loss from 0 to 6 dB. The driver has been employed in a 2:4 multiplexing and cable driving integrated circuit for 1.65 Gbps high-definition-multimedia-interface and digital-visual-interface application to drive up to 7 m 24-American-wire-gauge cable. Fabricated in 180 nm SiGe BiCMOS technology, the transmitter consumes 68.6 mW for 6 dB pre-emphasis under 3.3 V power supply.
  • loading
  • [1]
    N. Gupta, P. Bala, and V. K. Singh, “Area and power efficient 3.4 Gbps/channel HDMI transmitter with singleended structure,” 2013 26th Int. Conf. on VLSI Design and 12th Int. Conf. on Embedded Systems, Pune, pp.142–146, 2013.
    [2]
    J. Kim, J. Yang, S. Byun, et al., “A four-channel 3.125- Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer,” IEEE Journal of Solid-State Circuits, vol.40, no.2, pp.462–471, 2005. doi: 10.1109/JSSC.2004.841037
    [3]
    J. Liu and X. Lin, “Equalization in high-speed communication systems,” Circuits and Systems Magazine, IEEE, vol.4, no.2, pp.4–17, 2015.
    [4]
    J. E. Proesel and T. O. Dickson, “A 19-Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45-nm SOI CMOS,” 2011 Symposium on VLSI Circuits - Digest of Technical Papers, Honolulu, HI, pp.206–207, 2011.
    [5]
    A. Agrawal, J. F. Bulzacchelli, T. O. Dickson, et al., “A 19- Gb/s serial link receiver with both 4-Tap FFE and 5-Tap DFE functions in 45-nm SOI CMOS,” IEEE Journal of Solid-State Circuits, vol.47, no.12, pp.3220–3231, 2012. doi: 10.1109/JSSC.2012.2216412
    [6]
    P. A. Davies, “A 3.3/2.5 V-supply 2400 mV-swing single-ended SiGe BiCMOS driver with programmable preemphasis for 3-Gb/s data transmission over 75Ω coaxial cable,” IEEE Journal of Solid-State Circuits, vol.48, no.9, pp.2128– 2141, 2013. doi: 10.1109/JSSC.2013.2260096
    [7]
    P. Heydari, “Design and analysis of low-voltage current-mode logic buffers,” in Proc. of 4th Int. Symp. on Quality Electronic Design, San Jose, CA, pp.293–298, 2003.
    [8]
    P. S. Sahni, S. C. Joshi, N. Gupta, et al., “An equalizer with controllable transfer function for 6-Gb/s HDMI and 5.4-Gb/s displayport receivers in 28-nm UTBB-FDSOI,” IEEE Trans. VLSI Syst., vol.24, no.8, pp.2803–2807, 2016. doi: 10.1109/TVLSI.2016.2530680
    [9]
    HDMI Forum Inc., “High definition multimedia interface standard rev. 2.0,” http://hdmiforum.org, 2013-9-1.
    [10]
    H. Johnson and M. Graham, High Speed Signal Propagation: Advanced Black Magic, Englewood Cliffs: Prentice Hall, pp.147–148, 2003.
    [11]
    J. Seo, R. Ho, J. Lexau, et al., “High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90 nm CMOS,” 2010 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp.182–183, 2010.
    [12]
    Y. Lu, K. Jung, Y. Hidaka, et al., “Design and analysis of energy-efficient reconfigurable pre-emphasis voltage-mode transmitters,” IEEE Journal of Solid-State Circuits, vol.48, no.8, pp.1898–1909, 2013. doi: 10.1109/JSSC.2013.2258790
    [13]
    W. Bae, H. Ju, K. Park, et al., “A 6-to-32 Gb/s voltagemode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS,” 2016 IEEE Asian Solid-State Circuits Conference, Toyama, pp.241–244, 2016.
  • 加载中

Catalog

    通讯作者: 陈斌, bchen63@163.com
    • 1. 

      沈阳化工大学材料科学与工程学院 沈阳 110142

    1. 本站搜索
    2. 百度学术搜索
    3. 万方数据库搜索
    4. CNKI搜索

    Figures(9)  / Tables(1)

    Article Metrics

    Article views (787) PDF downloads(61) Cited by()
    Proportional views
    Related

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return