“TISA: Reconfigurable System for Template-Based Stream Computing,” Chinese Journal of Electronics, vol. 21, no. 4, pp. 594-598, 2012,
Citation: “TISA: Reconfigurable System for Template-Based Stream Computing,” Chinese Journal of Electronics, vol. 21, no. 4, pp. 594-598, 2012,

TISA: Reconfigurable System for Template-Based Stream Computing

Funds:  null
  • Received Date: 2011-11-01
  • Rev Recd Date: 2012-01-01
  • Publish Date: 2012-10-25
  • For High performance Digital signal process (HP-DSP) system with low-volume market, performance/ watt, flexibility and cost of design are becoming goals pursued by architects. This paper presents a template-based reconfigurable platformTISA-II, where application-specific stream computing system can be constructed fast, efficiently and conveniently. This paper describes the platform in terms of architecture, programming model, a hardware/software co-design flow, and our implementation. Finally, the paper evaluates TISA-II by a real applications HD H.264 encoding. The results are encouraging, TISA-II with 4 computing node achieves 50~100x speedup over embedded programmable processors (C64 DSP, MIPS) and 3x over dedicated stream processor (Storm), while consequently performance per watt that is also greater.
  • loading
  • S. Amarasinghe, Thies B. Architectures, “Languages and compilersfor the streaming domain”, Tutorial at 15th InternationalConference on Parallel Architectures and Compilation Techniques(PACT), New Orleans, LA, pp.4-6, 2003.
    Nan Wu et al., “Streaming HD H.264 encoder on programmableprocessors”, ACM Multimedia 2009, Beijing, pp.125-128, Oct.2009.
    Yale Patt, Jim Smith and Mateo Valero, “Fine- and coarse-grainreconfigurable computing”, Springer, pp.211-214, 2007.
    Nikolaos Bellas et al., “Mapping streaming architectures on reconfigurableplatforms”, ACM SIGARCH Computer ArchitectureNews 2, Vol.35, No.3, pp.24-27, June 2007.
    F. Bouwens et al., “Architectural exploration of the ADREScoarse-grained reconfigurable array”, in Proc. ARC 2007,LNCS, Vol.4419, pp.1-13, Springer, Heidelberg, 2007.
    Nan Wu et al., “A stream architecture supporting multiplestream execution models”, 10th ACSAC, LNCS 3740, pp.143-156, Singapore, Oct. 2005.
    B. Khailany et al., “A programmable 512GOPS stream processorfor signal, image, and video processing” IEEE ISSCC, SanFrancisco, pp.125-128, Feb. 2007.
    K. Kuusilinna et al., “Designing BEE: a hardware emulationengine for signal processing in low-power wireless applications”,EURASIP Journal on Applied Signal Processing, pp.34-45,2003.
    Sven Heithecker et al., “A high-end real-time digital film processingreconfigurable platform”, EURASIP Journal on EmbeddedSystems, pp.67-70, Article ID 85318, 2007.
  • 加载中

Catalog

    通讯作者: 陈斌, bchen63@163.com
    • 1. 

      沈阳化工大学材料科学与工程学院 沈阳 110142

    1. 本站搜索
    2. 百度学术搜索
    3. 万方数据库搜索
    4. CNKI搜索

    Article Metrics

    Article views (593) PDF downloads(1218) Cited by()
    Proportional views
    Related

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return