A Novel Boosted Charge Transfer Circuit for High Speed Charge Domain Pipelined ADC

Article Contents

Article Navigation > Chinese Journal of Electronics > 2012 > 21(4): 627-632

“A Novel Boosted Charge Transfer Circuit for High Speed Charge Domain Pipelined ADC,” Chinese Journal of Electronics, vol. 21, no. 4, pp. 627-632, 2012,

Citation:

“A Novel Boosted Charge Transfer Circuit for High Speed Charge Domain Pipelined ADC,” Chinese Journal of Electronics, vol. 21, no. 4, pp. 627-632, 2012,

“A Novel Boosted Charge Transfer Circuit for High Speed Charge Domain Pipelined ADC,” Chinese Journal of Electronics, vol. 21, no. 4, pp. 627-632, 2012,

Citation:

“A Novel Boosted Charge Transfer Circuit for High Speed Charge Domain Pipelined ADC,” Chinese Journal of Electronics, vol. 21, no. 4, pp. 627-632, 2012,

PDF( 925 KB)

A Novel Boosted Charge Transfer Circuit for High Speed Charge Domain Pipelined ADC

Received Date: 2011-10-01
Rev Recd Date: 2012-05-01
Publish Date: 2012-10-25

Abstract

Abstract

A novel Boosted charge transfer (BCT) circuit is proposed for Bucket-brigade devices (BBDs) based charge-domain (CD) pipelined Analog-to-digital converter (ADC). It can significantly lower the sensitivity on Process, voltage and temperature (PVT) variations of traditional BCT circuit, which can eliminate the Common mode (CM) charge control circuit in the existing CD pipelined ADC. With the proposed BCT circuit, a prototype ADC is realized in a 0.18μm CMOS process without using any common mode charge control techniques, with only 27mW power consumption at 1.8 V supply. It achieves Spurious free dynamic range (SFDR) of 67.7 dB, Signal-to-noiseand- distortion ratio (SNDR) of 55.8 dB and Effective number of bits (ENOB) of 9.0 for a 3.79 MHz input at full sampling rate. The Differential nonlinearity (DNL) is +0.5/?0.3 LSB, and the Integral nonlinearity (INL) is +0.7/?0.55 LSB.

FullText(HTML)

References(19)

References

A.M.A. Ali, M. Andy and D. Chris, et al., “A 16-bit 250-MS/s IF sampling pipelined ADC with background calibration”,IEEE J. Solid-State Circuits, Vol.45, No.12, pp.2602-2612, 2010.

R. Payne, M. Corsi, D. Smith, et al., “A 16-bit 100 to 160 MS/sSiGe BiCMOS pipelined ADC with 100 dBFS SFDR”, IEEE J.Solid-State Circuits, Vol.45, No.12, pp.2613-2622, 2010.

S. Lee and B. Song, “Digital-domain calibration of multistepanalog-to-digital converter”, IEEE J. Solid-State Circuits,Vol.27, No.12, pp.1679-1688, 1992.

E. Siragursa, I. Galton, “A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC”, IEEE J. Solid-State Circuits,Vol.39, No.12, pp.2126-2138, 2004.

B. Peter, K. Franz, K. Claus, et al., “A 14b 100MS/s digitallyself-calibrated pipelined ADC in 0.13μm CMOS”, Proc.of ISSCC, San Francisco, California, USA, pp.224-225, 2006.

B. Murmann and B. Boser, “A 12-b 75 MS/s pipelined ADCusing open-loop residue amplifier”, Proc. of ISSCC, San Francisco,California, USA, pp.330-331, 2003.

J. Li and U. Moon, “Background calibration techniques formulti-stage pipelined ADC’s with digital redundancy” IEEETrans. Circuits Syst. II, Vol.50, No.9, pp.531-538, 2003.

T. Sepke, J.K. Fiorenza, C.G. Sodini, et al., “Comparatorbasedswitched-capacitor circuits for scaled CMOS technologies”,Proc. of ISSCC, San Francisco, California, USA, pp.220-221, 2006.

L. Brooks and H.S. Lee, “A zero-crossing based 8-bit 200MS/spipelined ADC”, IEEE J. Solid-State Circuits, Vol.42, No.12,pp.2677-2687, 2007.

E.B. James, “Bucket brigade analog-to-digital converter”, USPatent, No.4072938, 1978.

C.N. Berglund, “Analog performance limitations of chargetransfer dynamic shift registers”, IEEE J. Solid-State Circuits,Vol.6, No.6, pp.391-394, 1971.

A. Michael, K. Edward, K. Jeffrey, et al., “A process-scalablelow-power cCharge-domain 13-bit pipeline ADC”, Proc. ofSymposium on VLSI Circuits, Honolulu, Hawaii, USA, pp.222-223, 2008.

W. FREY, “Bucket-brigade device with improved charge transfer”,IET Electronics Letters, Vol.9, No.25, pp.588-589, 1973.

J.H. Cai, H.S. Ren, C.Z. Hai, et al., “A charge coupledpipelined analog-to-digital converter”, Chinese patent,No.200910264739.2, 2009.

M. Yoshioka, M. Kudo, K. Gotoh, et al., “A 10b 125MS/s 40mWpipelined ADC in 0.18μm CMOS”, Proc. of ISSCC, San Francisco,California, USA, pp.282-283, 2005.

N.S. Pratap, K. Ashish, D. Chandrajit, et al., “20mW, 125Msps, 10bit pipelined ADC in 65nm standard digital CMOSprocess”, Proc. of IEEE CICC, San Jose, California, USA,pp.189-192, 2007.

C.H. Cheol, K.Y. Ju, K.W. Joo, et al., “A 10b 120 MS/s 108mW 0.18μm CMOS ADC with a PVT-insensitive current reference”,Analog Integrated Circuits and Signal Processing, Vol.61,No.58, pp.115-121, 2009.

K.H. Lee, S.W. Lee, Y.J. Kim, K.S. Kim and S.H. Lee, “Tenbit100 MS/s 24.2 mW 0.8mm 20.18μm CMOS pipeline ADCbased on maximal circuit sharing schemes”, Electronics Letters,Vol.45, No.25, pp.1296-1297, 2009.

C.S. Shin and G.C. Ahn, “A 10-bit 100-MS/s dual-channelpipelined ADC using dynamic memory effect cancellation technique”,IEEE Trans. Circuits Syst. II: Express briefs, Vol.58,No.5, pp.274-278, 2011.

Relative Articles

Supplements(0)

Cited By

Proportional views