Low-Latency SRT Division and Square Root Based on Remainder and Quotient Prediction

PENG Yuanxi; CHEN Jiyang; LEI Yuanwu; HE Tingting; DENG Ziye

doi:10.1049/cje.2016.10.024

Volume 26 Issue 1

Turn off MathJax

Article Contents

Article Navigation > Chinese Journal of Electronics > 2017 > 26(1): 58-64

PENG Yuanxi, CHEN Jiyang, LEI Yuanwu, et al., “Low-Latency SRT Division and Square Root Based on Remainder and Quotient Prediction,” Chinese Journal of Electronics, vol. 26, no. 1, pp. 58-64, 2017, doi: 10.1049/cje.2016.10.024

Citation:

PENG Yuanxi, CHEN Jiyang, LEI Yuanwu, et al., “Low-Latency SRT Division and Square Root Based on Remainder and Quotient Prediction,” Chinese Journal of Electronics, vol. 26, no. 1, pp. 58-64, 2017, doi: 10.1049/cje.2016.10.024

Citation:

PDF( 503 KB)

Low-Latency SRT Division and Square Root Based on Remainder and Quotient Prediction

doi: 10.1049/cje.2016.10.024

College of Computer, National University of Defense and Technology, Changsha 410073, China

Funds: This work is supported by Aerospace Science Fund of China (No.2013ZC88003), and National Natural Science Foundation of China (No.61402499).

More Information

Corresponding author: CHEN Jiyang (corresponding author) received the B.S. degree and M.S. degree in computer science in 2012 and 2015, respectively, from National University of Defense and Technology, China. Her research interests include high performance computing, multi-core architectures and on-chip networks. (Email:824750961@qq.com)
Received Date: 2014-11-24
Rev Recd Date: 2015-05-17
Publish Date: 2017-01-10

Abstract

Abstract

Sweeney, Robertson and Tocher (SRT) algorithm is a common and efficient way for division and square root (div/sqrt). We present to overlap two iterations into one cycle by predicting remainder and quotient. To reduce latency, redundant representation is used superiorly, as well as the use of a minimum redundancy factor. Division and square root can be integrated into one unit which causes a reduction in hardware cost. With 40nm technology library, the area of our architecture after layout design, is 37795μm², the power is 81.19mW and the delay is only 656ps. The cycles for double-precision division and square root are 17 and 16, respectively. Experiments show our architecture achieves small latency and high frequency, together with modest area and power.
- SRT,
- Predicting remainder and quotient,
- Minimum redundancy factor,
- Redundant representation,
- Division and square root

FullText(HTML)

References(24)

References

S.F. Oberman and J.M. Flynn, "Division algorithm and implementations", IEEE Transaction on Computers, Vol.46, No.8, pp.833-854, 1997.

D. Piso, J.A. Pineiro and J.D. Bruguem, "Analysis of the impact of different methods for division/square root computation in the performance of a superscalar microprocessor", Proc. of Euromicro Symposium on Digital System Design, Washington, USA, pp.218-225, 2002.

Coke, James, Baliga, et al., "Improvements in the Intel Core2 Penryn processor family architecture and microarchitecture", Intel Technology Journal, Vol.12, No.3, pp.179-184, 2008.

M.D. Ercegovac and T. Lang, Division and Square Root:Digit Recurrence Algorithms and Implementations, Kluwer Academic Publishers, Massachusetts, USA, 1994.

P. Soerquist and M. Leeser, "Area and performance tradeoffs in floating-point divide and square-root implementations", ACM Computing Surveys, Vol.28, No.3, pp.518-564, 1996.

S.F. Oberman and M.J. Flynn, "Minimizing the complexity of SRT tables", IEEE Transaction on Very Large Integration Systems, Vol.6, No.1, pp.141-149, 1998.

J. Frandrianto, "Algorithm for high-speed shared radix-8 division and radix-8 square root", Proc. of 9th Symposium on Computer Arithmetic, Santa Monica, CA, pp.68-75, 1989.

A. Nannarelli and T. Lang, "Lower power radix-4 combined division and square root", the International Conference on Computer Design, Austin, USA, pp.236-242, 1999.

N. Burgess and C.N. Hinds, "Design of the ARM VFP11 divide and square root synthesisable macrocell", Proc. of 18th IEEE Symposium on Computer Arithmetic, Montepellier, France, pp.87-96, 2007.

N. Burgess, "Retiming the ARM VFP-11 division and square root macrocell", Proc. of 41st Asilomar Conference on Signals, Systems and Computers, Monterey, USA, pp.363-366, 2007.

A. Amaricai and O. Boncalo, "SRT radix-2 dividers with (5,4) redundant representation of partial remainder", IEEE Transaction on Very Large Scale Integration Systems, Vol.23, No.5, pp.1016-1020, 2013.

M. Issad, M. Anane and H. Bessalah, "Inuence de la base sur les performances de la division SRT", Proc. of Journal Francophones La Algorithm Architecture, Dijon, France, pp.91-94, 2005. (in French)

T.N. Pham and E.E. Swartzlander, "Design of radix-4 SRT dividers in 65 nanometer CMOS technology", International Conference on Application-specific Systems, Architectures and Processors, Steamboat Springs, Colorado, pp.105-108, 2006.

M.R. Patel, D. Tejas, V.Shah, et al., "Implementation and analysis of interval SRT radix-2 division algorithm", International Journal of Electronics and Computer Science Engineering, Vol.1, No.3, pp.971-976, 1971.

N.R. Srivastava, "Radix 4 SRT division with quotient prediction and operand scaling", Europe Conference and Exhibition on Design, Automation and Test, Nice, France, pp.1-6, 2007.

M. Issad, H. Bessalah and N. Anane, "Higher radix and redundancy factor for floating point SRT division", IEEE Transactions on Very Large Scale Integration Systems, Vol.16, No.6, pp.774-779, 2008.

C.X. Wang, K.F. Zhang, K. Liu, et al., "Study on double precision floating point division", Microprocessors, Vol.6, No.6, pp.1-3, 2011. (in Chinese)

L. Wei and N. Alberto, "Power efficient division and square root unit", IEEE Transactions on Computers, Vol.61, No.8, pp.1059-1070, 2012.

A. Nannarelli, "Radix-16 combined division and square root unit", 201120th IEEE Symposium on Computer Arithmetic, Tuebingen, Germany, pp.169-176, 2011.

R. Ingo and T.G. Noll, "A digit-set-interleaved radix-8 division/square root kernel for double-precision floating point", 2010 International Symposium on System on Chip (SoC), Tampere, Finland, pp.150-153, 2010.

H. Wetter, E.M. Schwarz and J. Haess, "The IBM eServer z990 floating-point unit", IBM Journal of Research and Development, Vol.48, No.3, pp.311-322, 2004.

M.D. Ercegovac and T. Lang, Digital Arithmetic, Morgan Kaufmann Publishers, California, USA, 2003.

P. Kornerup, "Digit selection for SRT division and square root", IEEE Trans on Computers, Vol.54, No.3, pp.294-303, 2005.

D. Stevenson, "A national standard IEEE standard for binary floating-point arithmetic", ACM Sigplan Notices, Vol.22, No.2, pp.9-25, 1987.

Relative Articles

Supplements(0)

Cited By

Proportional views