Efficient Multi-rate Encoder of QC-LDPC Codes Based on FPGA for WIMAX Standard

WANG Xiumin; GE Tingting; LI Jun; SU Chen; HONG Fangfei

doi:10.1049/cje.2017.01.006

Volume 26 Issue 2

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WANG Xiumin, GE Tingting, LI Jun, et al., “Efficient Multi-rate Encoder of QC-LDPC Codes Based on FPGA for WIMAX Standard,” Chinese Journal of Electronics, vol. 26, no. 2, pp. 250-255, 2017, doi: 10.1049/cje.2017.01.006

Citation:

WANG Xiumin, GE Tingting, LI Jun, et al., “Efficient Multi-rate Encoder of QC-LDPC Codes Based on FPGA for WIMAX Standard,” Chinese Journal of Electronics, vol. 26, no. 2, pp. 250-255, 2017, doi: 10.1049/cje.2017.01.006

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Efficient Multi-rate Encoder of QC-LDPC Codes Based on FPGA for WIMAX Standard

doi: 10.1049/cje.2017.01.006

1.
College of Information Engineering, China Jiliang University, Hangzhou 310018, China;
2.
National Mobile Communications Research Laboratory, Southeast University, Nanjing 210018, China

Funds: This work is supported by the National Natural Science Foundation of China (No.61379027), and Jiangsu Postdoctoral Foundation (No.1302059B).

More Information

Corresponding author: GE Tingting (corresponding author) was born in 1990. She is pursuing a Master's Degree in signal processing in China Jiliang University. Her research interests include channel coding and decoding. (Email:836656440@qq.com)
Received Date: 2015-09-16
Rev Recd Date: 2016-06-10
Publish Date: 2017-03-10

Abstract

Abstract

An efficient multi-rate encoder for IEEE 802.16e LDPC codes which outperforms current single rate encoders with acceptable hardware consumption and efficient memory consumption is proposed. This design utilizes the common dual-diagonal structure in parity matrices to avoid the inverse matrix operation which requires extensive computations. Parallel Matrix-vector multiplication (MVM) units, bidirectional operation and storage compression are applied to this multi-rate encoder to increase the encoding speed and significantly reduce the quantity of memory bits required. The proposed encoding architecture also contributes to the design of multi-rate encoders whose parity matrices are dual-diagonally structured and have an Approximately lower triangular (ALT) form, such as in IEEE 802.11n and IEEE 802.22. Simulation results verified that the proposed encoder can efficiently work for all code rates specified in WIMAX standard. With a maximum clock frequency of 117 MHz, the encoder achieves 3 to 10 times higher throughput than prior works. The proposed encoder is capable to switch among six rates by adjusting the input parameter and it achieves the throughput up to 1Gbps.
- Encoder,
- Multi-rate,
- FPGA,
- Dual Diagonal,
- WIMAX

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References(14)

References

R.G. Gallager, "Low-density parity-check codes", IRE Trans. Inf. Theory, Vol.IT-8, No.1, pp.21-28, 1962.

D.J.C. MacKay and R.M. Neal, "Near Shannon limit performance of low density parity-check codes", IEEE Electron. Lett., Vol.32, pp.1645-1646, 1996.

IEEE Std 802.16eTM-2005 and IEEE Std 802.16TM-2004/Cor1-2005, "IEEE standard for local and metropolitan area networks part 16:Air interface for fixed and mobile broadband wireless access systems amendment 2:Physical and medium access control layers for combined fixed and mobile operation in licensed bands and corrigendum 1", 2006.

Yuan Ruijia, Bai Baoming and Tong Sheng, "FPGA-based design of LDPC encoder with throughput over 10 Gbps", J. Electron. Inf. Tech., Vol.33, No.12, pp.2942-2947, 2011.

Fei Wang, Peng Zhang and Changyin Liu, "FPGA implementation of a novel multi-rate QC-LDPC encoder for DTMB standard", Applied Mechanics and Materials, Vol.397-400, pp.2024-2027, 2013.

P. Zhang, C.Y. Liu and L.X. Jiang, "Efficient encoding of QC-LDPC codes based on rotate-left-accumulator circuits", Electron. Lett., Vol.49, No.13, pp.810-812, 2013.

Ahmed. Mahdi and Vassilis. Paliouras, "A low complexity-high throughput QC-LDPC encoder", IEEE Trans. Signal. Process., Vol.62, No.10, pp.2696-2708, 2014.

Huxing Zhang and Hongyang Yu, "Multi-rate QC-LDPC encoder", IEEE Circuits and Systems International Conference on Testing and Diagnosis, pp.1-4, 2009.

J.M.R. Vaz and J.A.B. Gerald, "A fast LDPC encoder/decoder for small/medium codes", Microelectron. J., Vol.44, No.10, pp.888-896, 2013.

Jeong Ki. KIM, Hyunseuk. YOO and Moon Ho. Lee, "Efficient encoding architecture for IEEE 802.16e LDPC codes", IEICE Trans. Fundamentals., Vol.E91-A, No.12, pp.3607-3611, 2008.

Alaa Aldin Al. Hariri, Fabrice. Monteiro, Loic. Sieler, et al., "Configurable and high-throughput architectures for quasi-cyclic low-density parity-check codes", 21st IEEE International Conference on Electronics, Circuits and Systems, pp.790-793, 2014.

Hemesh Yasotharan and Anthony Chan Carusone, "A flexible hardware encoder for systematic low-density parity-check codes", 52nd IEEE International Midwest Symposium on Circuits and Systems, pp.54-57, 2009.

Hang Yin, Weitao Du and Nanhao Zhu, "Design of improved LDPC encoder for CMMB based on SIMD architecture", 3rd International Conference on Information Science and Technology, Yangzhou, Jiangsu, pp.23-25, 2013.

Ming Zhao and Liang Li, "Online high-speed programmable quasi-cyclic LDPC code encoder structure", J Tsinghua Univ. (Sci & Tech), Vol.49, No.7, pp.1041-1044, 2009. (in Chinese).

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