GUO Jian, YU Zhinong, YAN Wei, et al., “Degradation and Self-recovery of Polycrystalline Silicon TFT CMOS Inverters Under NBTI Stress,” Chinese Journal of Electronics, vol. 28, no. 4, pp. 884, 2019, doi: 10.1049/cje.2019.03.004
Citation: GUO Jian, YU Zhinong, YAN Wei, et al., “Degradation and Self-recovery of Polycrystalline Silicon TFT CMOS Inverters Under NBTI Stress,” Chinese Journal of Electronics, vol. 28, no. 4, pp. 884, 2019, doi: 10.1049/cje.2019.03.004

Degradation and Self-recovery of Polycrystalline Silicon TFT CMOS Inverters Under NBTI Stress

doi: 10.1049/cje.2019.03.004
Funds:  This work is supported by the National Natural Science Foundation of China (No. 61675024).
More Information
  • Corresponding author: YU Zhinong (corresponding author) received the Ph.D. degree in School of the Electronic and Information Engineering from the Xi'an Jiaotong University in 2001. He is currently an associate professor in School of Optoelectronics and Beijing Engineering Research Center of Mixed Reality and Advanced Display, Beijing Institute of Technology. His research interests include flexible display, thin-film transistor, optical and optoelectronic thin film. (Email:znyu@bit.edu.cn)
  • Received Date: 2017-04-12
  • Rev Recd Date: 2018-03-22
  • Publish Date: 2019-07-10
  • Degradation and self-recovery of polycrystalline Silicon (poly-Si) Thin film transistor (TFT) by using complementary metal oxide semiconductor (CMOS) inverter were investigated. Under DC stress, degradation mechanisms were clarified by comparing the Voltage transfer characteristics (VTC) of fresh and stressed inverters. It is determined that Negative bias temperature instability (NBTI) of p-TFT dominates the degradation of the inverter under zero bias DC stress. After removing the stress, the VTC continues to be degraded, because the interface trap-states and the grain boundary trapstates increase due to hydrogen species diffusion. It is found out that the VTC is shifted to its right side severely with negative bias stress of VIN. The NBTI of p-TFT is enhanced and the NBTI of n-TFT also plays a role on the degradation. When removing the negative bias stress, the self-recovery of NBTI of nTFT and the continuing degradation of NBTI of p-TFT become competing mechanisms, together controlling the VTC after-stress behavior. Consequently, the continuing degradation of NBTI of p-TFT is restrained by selfrecovery of NBTI of n-TFT.
  • loading
  • C.Y Wu, Z.G Meng, J. Li, et al., “Display driving circuits made with MIUC poly-Si TFTs on glass substrate”, Acta Electronica Sinica, Vol.33, No.8, pp.1349-1352, 2005. (in Chinese)
    W. Wang and Z.G. Meng, “Low-temperature metal-induced laterally crystallized polycrystalline silicon material and device technology”, Acta Electronica Sinica, Vol.31, No.5, pp.662-666, 2003. (in Chinese)
    T. Serikawa and F. Omata, “High-quality polycrystalline Si TFTs fabricated on stainless-steel foils by using sputtered Si films”, IEEE Transactions on Electron Devices, Vol.49, No.5, pp.820-825, 2002.
    S. Maeda, S. Maegawa, T. Ipposhi, et al., “An analytical method of evaluating variation of the threshold voltage shift caused by the negative-bias temperature stress in poly-Si TFTs”, IEEE Transactions on Electron Devices, Vol.45, No.1, pp.165-172, 1998.
    J. Zhou, M.X. Wang and M. Wong, “Two-stage degradation of p-channel poly-Si thin film transistors under dynamic negative bias temperature stress”, IEEE Transactions on Electron Devices, Vol.58, No.9, pp.3034-3041, 2011.
    C.F. Hu, M.X. Wang, B. Zhang, et al., “Negative bias temperature instability dominated degradation of metalinduced laterally crystallized p-type polycrystalline silicon thin-film transistors”, IEEE Transactions on Electron Devices, Vol.56, No.4, pp.587-594, 2009.
    M.W. Ma, C.Y. Chen, C.J. Su, et al., “Characteristics of PBTI and hot carrier stress for LTPS-TFT with high-κ gate dielectric”, IEEE Electron Device Letters, Vol.29, No.2, pp.171-173, 2008.
    M. Xue, M.X. Wang, Z. Zhu, et al., “Degradation behaviors of metal-induced laterally crystallized n-type polycrystalline silicon thin-film transistors under DC bias stresses”, IEEE Transactions on Electron Devices, Vol.54, No.2, pp.225-232, 2007.
    H. Tango, T. Satoh and Y. Imai, “Hot-carrier-induced degradation of threshold voltage and transconductance in nchannel LDD and SD poly-Si TFTs”, Electronics Letters, Vol.38, No.20, pp.1227-1228, 2002.
    H.S. Wang, M.X. Wang, Z.Y. Yang, et al., “Stress power dependent self-heating degradation of metal-induced laterally crystallized n-type polycrystalline silicon thin-film transistors”, IEEE Transactions on Electron Devices, Vol.54, No.12, pp.3276-3284, 2007.
    Y. Uraoka, T. Hatayama, T. Fuyuki, et al., “Reliability of low temperature-silicon TFTs under inverter operation”, IEEE Transactions on Electron Devices, Vol.48, No.10, pp.2370-2374, 2001.
    Y. Toyota, M. Matsumura, M. Hatano, et al., “Degradation characteristics of n- and p-channel polycrystalline-silicon TFTs under CMOS inverter operation”, IEEE Transactions on Electron Devices, Vol.57, No.2, pp.429-436, 2010.
    W. Chen, M.X. Wang, Y. Zhou, et al., “Degradation of polycrystalline silicon TFT CMOS inverters under AC operation”, IEEE Transactions on Electron Devices, Vol.60, No.1, pp.295-300, 2013.
    C.Y. Chen, J.W. Lee, S.D. Wang, et al., “Negative bias temperature instability in low-temperature polycrystalline silicon thin-film transistors”, IEEE Transactions on Electron Devices, Vol.53, No.12, pp.2993-3000, 2006.
  • 加载中

Catalog

    通讯作者: 陈斌, bchen63@163.com
    • 1. 

      沈阳化工大学材料科学与工程学院 沈阳 110142

    1. 本站搜索
    2. 百度学术搜索
    3. 万方数据库搜索
    4. CNKI搜索

    Article Metrics

    Article views (494) PDF downloads(170) Cited by()
    Proportional views
    Related

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return