ZHOU Jianhua, S.K. PANG, ZOU Shichang, “Simulation Study of Novel Very-Shallow-Trench-Isolation Vertical Bipolar Transistors on PD SOI,” Chinese Journal of Electronics, vol. 20, no. 4, pp. 612-616, 2011,
Citation:
ZHOU Jianhua, S.K. PANG, ZOU Shichang, “Simulation Study of Novel Very-Shallow-Trench-Isolation Vertical Bipolar Transistors on PD SOI,” Chinese Journal of Electronics, vol. 20, no. 4, pp. 612-616, 2011,
ZHOU Jianhua, S.K. PANG, ZOU Shichang, “Simulation Study of Novel Very-Shallow-Trench-Isolation Vertical Bipolar Transistors on PD SOI,” Chinese Journal of Electronics, vol. 20, no. 4, pp. 612-616, 2011,
Citation:
ZHOU Jianhua, S.K. PANG, ZOU Shichang, “Simulation Study of Novel Very-Shallow-Trench-Isolation Vertical Bipolar Transistors on PD SOI,” Chinese Journal of Electronics, vol. 20, no. 4, pp. 612-616, 2011,
Two new structures with Very-shallowtrench-isolation (VSTI) for vertical bipolar transistors on thin top-Si PD SOI are proposed and their characterization is studied by 2-D simulations. These bipolar structures are compatible with 0.13μm SOI-CMOS process. The two proposed transistors exhibit good device performance with current gain of 64.34 and 89.7, fT of 24.04GHz and 22.8GHz, fmax of 23.78GHz and 40.31GHz, respectively.