A Dynamically Reconfigurable VLSI Architecture for H.264 Integer Transforms

The 4 × 4 integer transforms have been adopted in the MPEG-4 AVC /H.264 standard. In this paper, two novel signal flow graphs of the 4 × 4 forward and inverse transforms for H.264 are deduced. A new dynamically reconfigurable architecture without transpose memory for the integer transforms is proposed on the basis of the new SFGs. In comparison with the existing designs, the number of computing elements can be cut down through dynamically reconfiguration in our design. Our design is implemented with 0.18μm CMOS technology. Under a clock frequency of 200 MHz, this architecture allows the real-time processing of 4096×2048 at 30 fps with the area cost of 5140 gates and the power dissipation of 15.64mW.