Parameterized Integrated Power and Performance (PIPP) Model for Ultra High-Performance of TOPS level DSP

YANG Hui; CHEN Shuming; WU Tiebin

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Article Navigation > Chinese Journal of Electronics > 2013 > 22(4): 707-711

YANG Hui, CHEN Shuming, WU Tiebin, “Parameterized Integrated Power and Performance (PIPP) Model for Ultra High-Performance of TOPS level DSP,” Chinese Journal of Electronics, vol. 22, no. 4, pp. 707-711, 2013,

Citation:

YANG Hui, CHEN Shuming, WU Tiebin, “Parameterized Integrated Power and Performance (PIPP) Model for Ultra High-Performance of TOPS level DSP,” Chinese Journal of Electronics, vol. 22, no. 4, pp. 707-711, 2013,

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Parameterized Integrated Power and Performance (PIPP) Model for Ultra High-Performance of TOPS level DSP

School of Computer Science, National University of Defense Technology, Changsha 410073, China

Funds: This work is supported by the National Natural Science Foundation of China (No.61070036, No.61133007).

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Corresponding author: YANG Hui, CHEN Shuming
Received Date: 2012-05-01
Rev Recd Date: 2013-01-01
Publish Date: 2013-09-25

Abstract

Abstract

Amdahl's law is a simple and fundamental tool for understanding the evolution of performance as a function of parallelism. Following a recent trend on timing and power analysis of general purpose many-core chip using this law, we develop a novel PIP Panalytical model for evaluating the performance and power of hierarchical on-chip large-scale parallel architectures with the core number, super-node size, processing element number, and function unit number taken into consideration. We thereby investigate the influence of workload characteristics (Thread-level parallel TLP, Instruction-level parallel IL Pand Data-level parallel DLP) on resource allocation with the restriction of performance and power. The results provide some feasible options to design TOPS level DS Parchitecture as well as a theoretical basis for making the design more scalable.
- Hierarchical architecture,
- Data-level parallel (DLP),
- Thread-level parallel (TLP),
- Instruction-level parallel (ILP),
- Model

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References(11)

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