High Precision Mix-Signal Capacitor Mismatch Error Calibration Method for Charge-Domain Pipelined ADC

YU Zongguang; ZOU Jiaxuan; CHEN Zhenhai; WEI Jinghe; SU Xiaobo; ZHANG Hong

doi:10.1049/cje.2019.01.008

Volume 28 Issue 2

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Article Navigation > Chinese Journal of Electronics > 2019 > 28(2): 223-228

YU Zongguang, ZOU Jiaxuan, CHEN Zhenhai, et al., “High Precision Mix-Signal Capacitor Mismatch Error Calibration Method for Charge-Domain Pipelined ADC,” Chinese Journal of Electronics, vol. 28, no. 2, pp. 223-228, 2019, doi: 10.1049/cje.2019.01.008

Citation:

YU Zongguang, ZOU Jiaxuan, CHEN Zhenhai, et al., “High Precision Mix-Signal Capacitor Mismatch Error Calibration Method for Charge-Domain Pipelined ADC,” Chinese Journal of Electronics, vol. 28, no. 2, pp. 223-228, 2019, doi: 10.1049/cje.2019.01.008

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High Precision Mix-Signal Capacitor Mismatch Error Calibration Method for Charge-Domain Pipelined ADC

doi: 10.1049/cje.2019.01.008

1.
School of Microelectronic, Xidian University, Xi'an 710071, China;
2.
No. 58 Research Institute, China Electronic Technology Group Corporation, Wuxi 214035, China;
3.
School of Information Engineering, Huangshan University, Huangshan 245041, China;
4.
School of Electronics and Information Engineering, Xi'an Jiaotong University, Xi'an 710049, China

Funds: This work was supported by National Science Foundation of China (No.61704161) and Major Science and Technology Project in Anhui Province (No.18030901006).

Received Date: 2017-11-14
Rev Recd Date: 2017-12-25
Publish Date: 2019-03-10

Abstract

Abstract

A mix-signal high precision capacitor mismatch error calibration method for charge domain pipelined ADCs is proposed. The calibration method calibrates the capacitors one by one based on binary search. Charge errors caused by the capacitor mismatch in and between pipelined sub-stage circuits can be compensated by the proposed calibration method. Based on the proposed calibration method, a 14bit 250MS/s charge domain pipelined Analog-to-digital converter (ADC) is designed and realized in a 1P6M 0.18m CMOS process. Test results show the 14bit 250MS/s ADC achieves the signal-to-noise ratio of 70.7dBFS and the spurious free dynamic range of 84.6dB, with 70.1MHz single-tone sine wave input at 250MS/s, while the ADC core consumes the power consumption of 235mW and occupies an area of 3.2mm².
- Pipelined analog-to-digital converter,
- Charge domain (CD),
- For-ground calibration,
- Low power,
- Capacitor mismatch

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References(14)

References

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