Volume 31 Issue 4
Jul.  2022
Turn off MathJax
Article Contents
CAO Huamin, WANG Qi, LIU Fei, et al., “A Novel Plane-Based Control Bus Design with Distributed Registers in 3D NAND Flash Memories,” Chinese Journal of Electronics, vol. 31, no. 4, pp. 647-651, 2022, doi: 10.1049/cje.2021.00.283
Citation: CAO Huamin, WANG Qi, LIU Fei, et al., “A Novel Plane-Based Control Bus Design with Distributed Registers in 3D NAND Flash Memories,” Chinese Journal of Electronics, vol. 31, no. 4, pp. 647-651, 2022, doi: 10.1049/cje.2021.00.283

A Novel Plane-Based Control Bus Design with Distributed Registers in 3D NAND Flash Memories

doi: 10.1049/cje.2021.00.283
Funds:  This work was supported by the National Science and Technology Major Project of China (21-02)
More Information
  • Author Bio:

    (corresponding author) was born in 1987. She received the B.E. degree in integrated circuit engineering from Tsinghua University, China, in 2012. She is a Ph.D. candidate of Institute of Microelectronic, Chinese Academy of Sciences, and the University of Chinese Academy of Sciences. Her research interests include circuit design in memories and design for testability. (Email: caohuamin2005@163.com)

    received the Ph.D. degree from Fudan University, China, in 2005. He is a Professor in the Institute of Microelectronic, Chinese Academy of Sciences, and the University of Chinese Academy of Sciences. His research interests include novel memory design, error correction code, and mass storage techniques. (Email: wangqi1@ime.ac.cn)

    received the Ph.D. degree from Peking University, China, in 2003. He is a Professor in the Institute of Microelectronic, Chinese Academy of Sciences, and the University of Chinese Academy of Sciences. His research interests include novel memory design, phase lock loop, and analog digital converter. (Email: liufei@ime.ac.cn)

    received the Ph.D. degree from Peking University, China, in 2003. He is a Professor in the Institute of Microelectronic, Chinese Academy of Sciences, and the University of Chinese Academy of Sciences. His research interests include process, device characterization, and reliability of novel flash memory device. (Email: huozongliang@ime.ac.cn)

  • Received Date: 2021-08-21
  • Accepted Date: 2022-02-22
  • Available Online: 2022-03-18
  • Publish Date: 2022-07-05
  • This work presents a novel plane-based area-saving control bus design with distributed registers in 3D NAND flash memory. 99.47% control signal routing wires are reduced compared to the conventional control circuit design. Independent multi-plane read is compatible with the existing read operations thanks to the register addresses are reasonably assigned. Furthermore, power-saving register group address-based plane gating scheme is proposed which saves about 2.9 mW bus toggling power. A four-plane control bus design with 20K-bits registers has been demonstrated in field programmable gate array tester. The results show that the plane-based control bus design is beneficial to high-performance 3D NAND flash memory design.
  • loading
  • [1]
    D. Kang, M. Kim, C. J. Su, et al., “A 512Gb 3-bit/Cell 3D 6th-generation V-NAND flash memory with 82MB/s write throughput and 1.2Gb/s interface,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.216–218, 2019.
    [2]
    N. Shibata, K. Kanda, T. Shimizu, et al., “A 1.33-Tb 4-bit/cell 3-D flash memory on a 96-word-line-layer technology,” IEEE Journal of Solid-State Circuits, vol.55, no.1, pp.178–188, 2020. doi: 10.1109/JSSC.2019.2941758
    [3]
    D. Kim, H. Kim, S. Yun, et al., “A 1Tb 4b/Cell NAND flash memory with t$_{PROG}$=2ms, t${_R}$=110us and 1.2Gb/s high-speed IO rate,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.218–220, 2020.
    [4]
    Y. B. Wakchaure, A. S. Madraswala, D. J. Pelster, et al., “Independent NAND memory operations by plane,” Patent, 10877696 B2, USA, 2020-12-29.
    [5]
    A. Silvagni, G. Fusillo, R. Ravasio, et al., “An overview of logic architectures inside flash memory devices,” Proceedings of the IEEE, vol.91, no.4, pp.569–580, 2003. doi: 10.1109/JPROC.2003.811707
    [6]
    L. G. Fasoli., “System and method of controlling a three-dimensional memory,” Patent, 7149119 B2, USA, 2006-12-12.
  • 加载中

Catalog

    通讯作者: 陈斌, bchen63@163.com
    • 1. 

      沈阳化工大学材料科学与工程学院 沈阳 110142

    1. 本站搜索
    2. 百度学术搜索
    3. 万方数据库搜索
    4. CNKI搜索

    Figures(6)  / Tables(2)

    Article Metrics

    Article views (378) PDF downloads(27) Cited by()
    Proportional views
    Related

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return