Citation: | LIANG Bin, WEN Yi, CHEN Jianjun, et al., “Technology Dependency of TID Response for a Custom Bandgap Voltage Reference in 65 nm to 28 nm Bulk CMOS Technologies,” Chinese Journal of Electronics, vol. 32, no. 6, pp. 1286-1292, 2023, doi: 10.23919/cje.2021.00.448 |
[1] |
V. Gromov, A. J. Annema, R. Kluit, et al., “A radiation hard bandgap reference circuit in a standard 0.13 μm CMOS technology,” IEEE Transactions on Nuclear Science, vol.54, no.6, pp.2727–2733, 2007. doi: 10.1109/TNS.2007.910170
|
[2] |
D. M. Fleetwood, “Total ionizing dose effects in MOS and low-dose-rate-sensitive linear-bipolar devices,” IEEE Transactions on Nuclear Science, vol.60, no.3, pp.1706–1730, 2013. doi: 10.1109/TNS.2013.2259260
|
[3] |
R. L. Pease, “Total ionizing dose effects in bipolar devices and circuits,” IEEE Transactions on Nuclear Science, vol.50, no.3, pp.539–551, 2003. doi: 10.1109/TNS.2003.813133
|
[4] |
A. Privat, P. W. Davis, H. J. Barnaby, et al., “Total dose effects on negative and positive low-dropout linear regulators,” IEEE Transactions on Nuclear Science, vol.67, no.7, pp.1332–1338, 2020. doi: 10.1109/TNS.2020.2977296
|
[5] |
C. M. Andreou, D. M. Gonzalez-Castaño, S. Gerardin, et al., “Low-power, subthreshold reference circuits for the space environment: evaluated with γ-rays, X-rays, protons and heavy ions,” Electronics, vol.8, no.5, article no.articleno.562, 2019. doi: 10.3390/electronics8050562
|
[6] |
D. M. Colombo, A. Rosseto, G. I. Wirth, et al., “Total dose effects on voltage references in 130-nm CMOS technology,” IEEE Transactions on Device and Materials Reliability, vol.18, no.1, pp.27–36, 2018. doi: 10.1109/TDMR.2017.2787906
|
[7] |
A. S. Cardoso, P. S. Chakraborty, N. Karaulac, et al., “Single-event transient and total dose response of precision voltage reference circuits designed in a 90-nm SiGe BiCMOS technology,” IEEE Transactions on Nuclear Science, vol.61, no.6, pp.3210–3217, 2014. doi: 10.1109/TNS.2014.2358078
|
[8] |
T. Vergine, M. De Matteis, S. Michelis, et al., “A 65 nm rad-hard bandgap voltage reference for LHC environment,” IEEE Transactions on Nuclear Science, vol.63, no.3, pp.1762–1767, 2016. doi: 10.1109/TNS.2016.2550581
|
[9] |
E. Boufoss, P. Gérard, P. Simon, et al., “High temperature and radiation hard CMOS SOI sub-threshold voltage reference,” in 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Monterey, CA, USA, pp.1–2, 2013.
|
[10] |
K. J. Shetler, N. M. Atkinson, W. T. Holman, et al., “Radiation hardening of voltage references using chopper stabilization,” IEEE Transactions on Nuclear Science, vol.62, no.6, pp.3064–3071, 2015. doi: 10.1109/TNS.2015.2499171
|
[11] |
Y. Piccin, H. Lapuyade, Y. Deval, et al., “Radiation-hardening technique for voltage reference circuit in a standard 130 nm CMOS technology,” IEEE Transactions on Nuclear Science, vol.61, no.2, pp.967–974, 2014. doi: 10.1109/TNS.2014.2312269
|
[12] |
J. J. Chen, Y. Q. Chi, B. Liang, et al., “ASET and TID characterization of a radiation hardened bandgap voltage reference in a 28-nm bulk CMOS technology,” IEEE Transactions on Nuclear Science, vol.69, no.5, pp.1141–1147, 2022. doi: 10.1109/TNS.2022.3152496
|
[13] |
J. J. Chen, S. M. Chen, B. Liang, et al., “Simulation study of the layout technique for P-hit single-event transient mitigation via the source-isolation,” IEEE Transactions on Device and Materials Reliability, vol.12, no.2, pp.501–509, 2012. doi: 10.1109/TDMR.2012.2191971
|
[14] |
J. J. Chen, S. M. Chen, Y. B. He, et al., “Novel layout technique for single-event transient mitigation using dummy transistor,” IEEE Transactions on Device and Materials Reliability, vol.13, no.1, pp.177–184, 2013. doi: 10.1109/TDMR.2012.2227261
|
[15] |
J. J. Chen, S. M. Chen, Y. B. He, et al., “Novel layout technique for N-hit single-event transient mitigation via source-extension,” IEEE Transactions on Nuclear Science, vol.59, no.6, pp.2859–2866, 2012. doi: 10.1109/TNS.2012.2212457
|
[16] |
J. J. Chen, J. T. Yu, P. F. Yu, et al., “Characterization of the effect of pulse quenching on single-event transients in 65-nm twin-well and triple-well CMOS technologies,” IEEE Transactions on Device and Materials Reliability, vol.18, no.1, pp.12–17, 2018. doi: 10.1109/TDMR.2018.2797074
|
[17] |
J. J. Chen, S. M. Chen, Y. Q. Chi, et al., “Characterization of single-event transient pulse quenching among dummy gate isolated logic nodes in 65 nm twin-well and triple-well CMOS technologies,” IEEE Transactions on Nuclear Science, vol.62, no.5, pp.2302–2309, 2015. doi: 10.1109/TNS.2015.2469740
|
[18] |
X. Yu, W. Lu, X. L. Li, et al., “Total ionizing dose effect and failure mechanism of digital signal processor,” Chinese Journal of Electronics, vol.30, no.5, pp.986–990, 2021. doi: 10.1049/cje.2021.07.010
|
[19] |
B. K. Liu, Y. D. Li, L. Wen, et al., “Analysis of dark signal degradation caused by 1 MeV neutron irradiation on backside-illuminated CMOS image sensors,” Chinese Journal of Electronics, vol.30, no.1, pp.180–184, 2021. doi: 10.1049/cje.2020.12.002
|