Citation: | DAI Lan, GUO Hong, LIN Qipeng, et al., “An In-Memory-Computing Design of Multiplier Based on Multilevel-Cell of Resistance Switching Random Access Memory,” Chinese Journal of Electronics, vol. 27, no. 6, pp. 1151-1157, 2018, doi: 10.1049/cje.2018.08.006 |
J. Von Neumann, “First draft of a report on the EDVAC”, IEEE Annals of the History of Computing, Vol.15, No.4, pp.27-75, 1993.
|
S. Borkar and A.A. Chien, The future of microprocessors, ACM, Vol.54, No.6, pp.46-53, 2011.
|
L.O. Chua and S.M. Kang, “Memristive devices and systems”, Proceeding of the IEEE, Vol.64, No.2, pp.209-223, 1976.
|
W. Wang, J. Chen, Q.H. Yu, et al., “A research of two kinds of mechanism and performance improvement of resistive switching access memory”, Acta Electronica Sinica, Vol.45, No.4, pp.989-999, 2017. (in Chinese)
|
D.B. Strukov, G.S. Snider, D.R. Williams, et al., “The missing memristor found”, Nature, Vol.453, No.7191, pp.80-83, 2008.
|
B. Chen, F. Cai, J. Zhou, et al., “Efficient in-memory computing architecture based on crossbar arrays”, IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA, pp.17.5.1-17.5.4, 2015.
|
M.S. Ebrahimi, G. Hills, M.M. Sabry, et al., “Monolithic 3D integration advances and challenges: From technology to system levels”, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conf. IEEE, Millbrace, CA, USA, pp.1-2, 2014.
|
H. Li and Y. Chen, “An overview of non-volatile memory technology and the implication for tools and architectures”, Design, Automation, Test in Europe Conference, Exhibition, IEEE, Nice, France, pp.731-736, 2009.
|
L. Xiao and R.B. Lu, “A fully complex-valued gradient neural network for rapidly computing complex-valued linear matrix equations”, Chinese Joumal of Electronics, Vol.26, No.6, pp.1194-1197, 2017.
|
H.S.P. Wong, H.Y. Lee, S. Yu, et al., “Metal-oxide RRAM”, Proceedings of the IEEE, Vol.100, No.6, pp.1951-1970, 2012.
|
Y.C. Yang, F. Pan, Q. Liu, et al., “Full room-temperaturefabricated nonvolatile resistive memory for ultrafast and highdensity memory application”, Nano Letters, Vol.9, No.4, pp.1636-1643, 2009.
|
D. Jaina, K. Sethi and R. Panda, “Vedic Mathematics Based Multiply Accumulate Unit”, International Conference on Computational Intelligence and Communication Systems, IEEE Computer Society, Gwalior, India, pp.754-757, 2011.
|
S.R. Huddar, S.R. Rupanagudi, M. Kalpana, et al., “Novel high speed vedic mathematics multiplier using compressors”, International Multi-Conference on Automation, Computing, Communication, Control and Compressed Sensing, IEEE, Kottayam, India, pp.465-469, 2013.
|
G.G. Kumar and S.K. Sahoo, “Implementation of a high speed multiplier for high-performance and low power applications”, International Symposium on VLSI Design and Test, IEEE, Ahmedabad, India, pp.1-4, 2005.
|
W.C. Chien, Y.C. Chen, K.P. Chang, et al., “Multi-level operation of fully CMOS compatible WOx resistive random access memory (RRAM)”, IEEE International Memory Workshop,Monterey, CA, USA, pp.1-2, 2009.
|
Z. Jiang, Y. Wu, S. Yu, et al., “A compact model for metaloxide resistive random access memory with experiment verification”, IEEE Transactions on Electron Devices Meeting (IEDM), Vol.63, No.5, pp.1884-1892, 2016.
|
B.C Paul, S. Fujita and M. Okajima, “ROM-based logic (RBL) design: A low-power 16bit multiplier”, IEEE Journal of SolidState Circuits, Vol.44, No.11, pp.2935-2942, 2009.
|
Y.L. Song, Y. Meng, X.Y. Xue, et al., “Reliability significant improvement of resistive switching memory by dynamic selfadaptive write method”, Symposium on VLSI Technology, Kyoto, Japan, pp.T102-T103, 2013.
|
Y. Tian, B. Yuan and T.L. Li, “A massive and heterogeneous data storage and sharing strategy for internet of things”, Acta Electronica Sinica, Vol.44, No.2, pp.247-257, 2016. (in Chinese)
|