Volume 30 Issue 3
May  2021
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GE Chenyang, YAO Huimin, ZHOU Yanhui, DENG Pengchao. VLSI Design for High-Precision Three-Dimensional Depth Perception Chip[J]. Chinese Journal of Electronics, 2021, 30(3): 556-560. doi: 10.1049/cje.2021.04.009
Citation: GE Chenyang, YAO Huimin, ZHOU Yanhui, DENG Pengchao. VLSI Design for High-Precision Three-Dimensional Depth Perception Chip[J]. Chinese Journal of Electronics, 2021, 30(3): 556-560. doi: 10.1049/cje.2021.04.009

VLSI Design for High-Precision Three-Dimensional Depth Perception Chip

doi: 10.1049/cje.2021.04.009
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This work is supported by the National Natural Science Foundation of China (No.61627811).

  • Received Date: 2016-11-08
  • This paper presents a Very large scale integration (VLSI) design method for Three-dimensional (3D) depth perception chip based on infrared coding structure light. The primary sub-modules on the chip contain the speckle pattern preprocessing module, block-matching disparity estimation, depth mapping and post-processing. The chip employs pipelining technology, and after Application specific integrated circuit (ASIC) verification, it proves that our chip has more advantages in performance of depth precision (12bits, 1mm @ 1m), image resolution (1280×960), time delay (less than 17ms), range limit (0.4~6m). It also can generate more stable and smooth depth map in real-time, which can be used in 3D recognition, motion capture or scene perception.
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