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PRAVINAH Shasidharan, SELVAKUMAR Mariappan, JIA XIN Lim, et al., “A 5 mW 1-to-5 GHz Multiband Ladder CMOS Mixer Employing Transconductance Tuning Mechanism Achieving IIP3 of 27 dBm,” Chinese Journal of Electronics, in press, doi: 10.23919/cje.2022.00.028, 2023.
Citation: PRAVINAH Shasidharan, SELVAKUMAR Mariappan, JIA XIN Lim, et al., “A 5 mW 1-to-5 GHz Multiband Ladder CMOS Mixer Employing Transconductance Tuning Mechanism Achieving IIP3 of 27 dBm,” Chinese Journal of Electronics, in press, doi: 10.23919/cje.2022.00.028, 2023.

A 5 mW 1-to-5 GHz Multiband Ladder CMOS Mixer Employing Transconductance Tuning Mechanism Achieving IIP3 of 27 dBm

doi: 10.23919/cje.2022.00.028
Funds:  This work is supported by CREST under grant number PCEDEC/6050415, Ministry of Higher Education Malaysia for Fundamental Research Grant Scheme with Project Code FRGS/1/2019/TK04/USM/02/14 and QEDT Venture
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  • Author Bio:

    Shasidharan PRAVINAH was born in Kuala Lumpur, Malaysia. She received the Bsc.Eng. degree in electrical system engineering from University of Malaysia Perlis (UniMAP), Msc degree from University of Malaya (UM). She is currently pursuing her Ph.D. in microelectronics system engineering at Universiti Sains Malaysia (USM). Her research interests include CMOS Analog Design, Oscillators, Phase Locked Loop and RF Transceivers. (Email: pravinah.shasidharan@student.usm.my)

    Mariappan SELVAKUMAR was born in Butterworth, Penang, Malaysia. He received the B.Eng.Tech. degree in electrical engineering technology from Technical University of Malaysia Melaka (Utem) and obtained his Ph.D degree in the field of microelectronic engineering from Universiti Sains Malaysia (USM).He serves as a consultant for QRF Solutions Sdn Bhd and Co-Founder of QEDT, a Malaysian IC Design start-up company based in Penang. His research interests include CMOS analog IC and RFIC design. (Email: selva@qedt.com.my)

    Lim JIA XIN was born in Georgetown, Penang, Malaysia..She received the Bsc.Eng. degree in electrical engineering technology from Coventry University (CU), Msc degree from Universiti Sains Malaysia (USM).She works as a Structural Design Engineer at Intel based in Penang. Her research interest include RF Transceiver and CMOS Digital Integrated Design. (Email: jiaxin.lim1910@student.usm.my)

    Rajendran JAGADHESWARAN was born in Penang. He received the B.Eng. degree (Hons.) from the Universiti Sains Malaysia, in 2004, the M.Eng. degree (telecommunication) from Multimedia University, in 2011, and the Ph.D. degree in the field of microelectronic engineering from the University of Malaya, in 2015. He was with Laird Technologies as an Antenna Designer, followed by serving Motorola Technology as an Research and Development Engineer, from 2005 to 2007, where he was working on a mobile phone receiver systems. In 2008, he joined BroadComm as an MMIC Designer, working mainly on GaAs-based power amplifier, LNA, and gain blocks, where he was elevated to the rank of Principal Engineer later. In 2015, he joined Silterra Malaysia, working on CMOS RFIC Design, device modeling, and power MOS. He is currently serving as a Senior Lecturer for Collaborative Microelectronic Design Excellence Centre (CEDEC) and the School of Electrical and Electronic Engineering, Universiti Sains Malaysia, where he is working on CMOS analog IC Design, CMOS radio frequency (RF) IC design, and GaAs monolithic microwave integrated circuit (MMIC) design. He has published 70 research articles, mainly journals, and holds one U.S. patent. He was a recipient of the IEEE Circuit and System Outstanding Doctoral Dissertation Award, in 2015. He served as the Chairman for IEEE ED /MTT/SSC Penang Chapter, in 2011 and 2018. (Email: jaga.rajendran@usm.my)

    Aridas NARENDRA KUMAR was born in Kulim, Kedah. He received the Ph.D. degree in electrical engineering from RWTH Aachen University, Aachen, Germany. In 1999, he was with Motorola Solutions as the Principal Staff Engineer (product development and testing). He has been appointed as a Visiting Professor at Istanbul University, since January 2011. Since August 2013, he has also been with the Department of Electrical Engineering, University of Malaya, as an Associate Professor. He is driving Industry 4.0 research activities with the collaboration of RWTH Aachen University, Germany, and supporting industryuniversity relationships in digital transformation. In June 2009, he has served as a Reviewer of IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES and IET Circuit, Devices and Systems. (Email: narendra.k@um.edu.my)

  • Available Online: 2023-04-23
  • This paper presents a CMOS mixer employing a transconductance tuning (TCT) mechanism to achieve wideband, low power, high gain, and high linearity. The ladder CMOS mixer consists of one current source, one differential amplifier and two differential low noise switching stage. The TCT technique optimizes the optimum drain current requirement and the output voltage at the voltage control oscillator node and the RF output node, thus producing a balance linearity performance with low power consumption for 4 GHz operating bandwidth. The wideband linearity performance is achieved without inductors, thus reducing the size of the chip significantly to 0.5 mm2. Designed in 180-nm CMOS, the TCT mixer operates from 1 GHz to 5 GHz with a 1.2 V supply voltage, resulting in a highest measured result performances of the third-order input intercept point (IIP3) of 35.97 dBm across the local oscillator (LO) input power and 27.2 dBm across the RF input power. The highest measured conversion gain (CG) encapsulated around 29.17 dB under RF input power whereas 22.27 dB across the LO input power at center frequency of 3 GHz. The TCT mixer provides full mixing operation which achieves the measured noise figure (NF) below 5 dB across the IF output frequency. Moreover, the port-to-port isolation less than −30 dB has also been achieved across the RF operating bandwidth. The total power consumption, PDC of the TCT chip is 5 mW. The operating bandwidth of the TCT mixer qualifies it to be integrated into a multiband 5G New Radio receiver system.
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