Volume 33 Issue 2
Mar.  2024
Turn off MathJax
Article Contents
Ruiming XU, Zhongjie GUO, Suiyang LIU, et al., “Global Ramp Uniformity Correction Method for Super-Large Array CMOS Image Sensors,” Chinese Journal of Electronics, vol. 33, no. 2, pp. 415–422, 2024 doi: 10.23919/cje.2022.00.397
Citation: Ruiming XU, Zhongjie GUO, Suiyang LIU, et al., “Global Ramp Uniformity Correction Method for Super-Large Array CMOS Image Sensors,” Chinese Journal of Electronics, vol. 33, no. 2, pp. 415–422, 2024 doi: 10.23919/cje.2022.00.397

Global Ramp Uniformity Correction Method for Super-Large Array CMOS Image Sensors

doi: 10.23919/cje.2022.00.397
More Information
  • Author Bio:

    Ruiming XU is pursuing the M.S. degree in Xi’an University of Technology. His current research interests include high performance mixed signal integration circuit design. (Email: rmxu@stu.xaut.edu.cn)

    Zhongjie GUO received the B.S. and M.S. degrees from Xidian University, China, in 2004 and 2007, respectively, and Ph.D. degree in microelectronics engineering from Xi’an Microelectronic Technology Institute, China, in 2012. His current research interests include high performance mixed signal integration circuit design. (Email: zjguo@xaut.edu.cn)

    Suiyang LIU was born in Xi’an, Shaanxi Province, China, in 1997. She received the B.S. degree in integrated circuit design and integrated systems from Xi’an University of Technology in 2019 and the M.S. degree in electronic science and technology from Xi’an University of Technology in 2022. Her research interests include organic photodetectors, TSV, and CMOS image sensors. (Email: 1220310003@stu.xaut.edu.cn)

    Ningmei YU received the B.S. degree in electronic engineering from the Xi’an University of Technology, Xi’an, China, in 1986, and the M.S. and Ph.D. degrees in electronic engineering from Tohoku University, Sendai, Japan, in 1996 and 1999, respectively. She is currently a Professor with the Department of Electric Engineering, Xi’an University of Technology. Her current research interests include very large scale integration circuit design. (Email: yunm@xaut.edu.cn)

  • Corresponding author: Email: zjguo@xaut.edu.cn
  • Received Date: 2022-11-22
  • Accepted Date: 2023-02-14
  • Available Online: 2023-07-15
  • Publish Date: 2024-03-05
  • Aiming at the problem of the non-uniformity of the ramp signal in the super-large array CMOS (complementary metal-oxide semiconductor) image sensors, a ramp uniformity correction method for CMOS image sensors is proposed in this paper. Based on the error storage technique, the ramp non-uniformity error is stored. And the input ramp signal of each column is shifted by level-shifting technique to eliminate the ramp non-uniformity error. Based on the 55 nm-1P4M CMOS process, this paper has completed the detailed circuit design and comprehensive simulation verification of the proposed method. Under the design conditions that the voltage range of the ramp signal is 1.4 V, the slope of the ramp signal is 71.908 V/ms, the number of pixels is 8192 (H) × 8192 (V), and a single pixel size is 10 μm, the correction method proposed in this paper reduces the ramp non-uniformity error from 7.89 mV to 36 μV. The differential non-linearity of the ramp signal is +0.0013/−0.004 LSB and the integral non-linearity is +0.045/−0.021 LSB. The ramp uniformity correction method proposed in this paper reduces the ramp non-uniformity error by 99.54% on the basis of ensuring the high linearity of the ramp signal, without significantly increasing the chip area and without introducing additional power consumption. The column fixed-pattern noise is reduced from 1.9% to 0.01%. It provides theoretical support for the design of high-precision CMOS image sensors.
  • loading
  • [1]
    M. Teymouri, “A highly linear and high-accurate CMOS image sensor,” Analog Integrated Circuits and Signal Processing, vol. 102, no. 1, pp. 91–96, 2020. doi: 10.1007/s10470-019-01553-4
    [2]
    K. Park, S. Yeom, and S. Y. Kim, “Ultra-low power CMOS image sensor with two-step logical shift algorithm-based correlated double sampling scheme,” IEEE Transactions on Circuits and Systems I:Regular Papers, vol. 67, no. 11, pp. 3718–3727, 2020. doi: 10.1109/TCSI.2020.3012980
    [3]
    M. F. Snoeij, A. J. P. Theuwissen, K. A. A. Makinwa, et al., “A CMOS imager with column-level ADC using dynamic column fixed-pattern noise reduction,” IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 3007–3015, 2006. doi: 10.1109/JSSC.2006.884866
    [4]
    K. V. Tham, C. Ulaganathan, N. Nambiar, et al., “PVT compensation for Wilkinson single-slope measurement systems,” IEEE Transactions on Nuclear Science, vol. 59, no. 5, pp. 2444–2450, 2012. doi: 10.1109/TNS.2012.2212722
    [5]
    G. Renaud, M. J. Barragan, A. Laraba, et al., “A 65 nm CMOS ramp generator design and its application towards a BIST implementation of the reduced-code static linearity test technique for pipeline ADCs,” Journal of Electronic Testing:Theory and Applications, vol. 32, no. 4, pp. 407–421, 2016. doi: 10.1007/s10836-016-5599-8
    [6]
    A. A. Noorwali, S. M. Qasim, A. S. Doost, et al., “A 16-bit 4 MSPS DAC for lock-in amplifier in 65nm CMOS,” in 2016 IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference, St. Petersburg, Russia, pp.297–301, 2016.
    [7]
    X. Cheng, X. Y. Zeng, and Q. Feng, “Analysis and improvement of ramp gain error in single-ramp single-slope ADCs for CMOS image sensors,” Microelectronics Journal, vol. 58, pp. 23–31, 2016. doi: 10.1016/j.mejo.2016.10.006
    [8]
    Q. H. Zhang, N. Ning, J. Li, et al., “A high area-efficiency 14-bit SAR ADC with hybrid capacitor DAC for array sensors,” IEEE Transactions on Circuits and Systems I:Regular Papers, vol. 67, no. 12, pp. 4396–4408, 2020. doi: 10.1109/TCSI.2020.2998473
    [9]
    F. S. Dumitru, C. R. Ilie, and M. Enachescu, “Exploring the effect of segmentation on INL and DNL for a 10-bit DAC,” in 2020 International Semiconductor Conference, Sinaia, Romania, pp.161–164, 2020.
    [10]
    S. Y. Park and H. J. Kim, “CMOS image sensor with two-step single-slope ADC using differential ramp generator,” IEEE Transactions on Electron Devices, vol. 68, no. 10, pp. 4966–4971, 2021. doi: 10.1109/TED.2021.3102003
    [11]
    R. S. Prasobh Sankar, L. Asish, and B. Bhuvan, “Design of stable error-correction ramp generators considering process and run-time variations,” in 2019 IEEE Asia Pacific Conference on Circuits and Systems, Bangkok, Thailand, pp.257–260, 2019.
    [12]
    K. M. Nie, W. Zha, X. L. Shi, et al., “A single slope ADC with row-wise noise reduction technique for CMOS image sensor,” IEEE Transactions on Circuits and Systems I:Regular Papers, vol. 67, no. 9, pp. 2873–2882, 2020. doi: 10.1109/TCSI.2020.2979321
    [13]
    Z. J. Guo, N. M. Yu, and L. S. Wu, “Research on column FPN and black level calibration in large array CMOS image sensor,” Chinese Journal of Electronics, vol. 30, no. 2, pp. 268–274, 2021. doi: 10.1049/cje.2021.02.004
    [14]
    J. Lee, I. Baek, D. Yang, et al., “On-chip FPN calibration for a linear-logarithmic APS using two-step charge transfer,” IEEE Transactions on Electron Devices, vol. 60, no. 6, pp. 1989–1994, 2013. doi: 10.1109/TED.2013.2259236
    [15]
    Z. W. Liu, J. T. Xu, X. L. Wang, et al., “A fixed-pattern noise correction method based on gray value compensation for TDI CMOS image sensor,” Sensors, vol. 15, no. 9, pp. 23496–23513, 2015. doi: 10.3390/s150923496
    [16]
    C. Z. Li, B. G. Han, J. He, et al., “A highly linear CMOS image sensor design based on an adaptive nonlinear ramp generator and fully differential pipeline sampling quantization with a double auto-zeroing technique,” Sensors, vol. 20, no. 4, article no. 1046, 2020. doi: 10.3390/s20041046
    [17]
    J. W. Wei, X. Li, L. Sun, et al., “A 63.2μw 11-bit column parallel single-slope ADC with power supply noise suppression for CMOS image sensors,” in 2020 IEEE International Symposium on Circuits and Systems, Seville, Spain, pp.1–4, 2020.
    [18]
    D. Levski, M. Wany, and B. Choubey, “Ramp noise projection in CMOS image sensor single-slope ADCs,” IEEE Transactions on Circuits and Systems I:Regular Papers, vol. 64, no. 6, pp. 1380–1389, 2017. doi: 10.1109/tcsi.2017.2662950
    [19]
    S. D. Huang, W. G. Lu, Y. Zhou, et al., “An automatic slope-calibrated ramp generator for single-slope ADCs,” in 2019 IEEE 13th International Conference on ASIC, Chongqing, China, pp.1–4, 2019.
    [20]
    J. Bogaerts, R. Lafaille, M. Borremans, et al., “6.3 105×65 mm2 391mpixel CMOS image sensor with >78 db dynamic range for airborne mapping applications,” in 2016 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, pp.114–115, 2016.
    [21]
    T. Arai, T. Yasue, K. Kitamura, et al., “6.9 a 1.1 μm 33 Mpixel 240 fps 3D-stacked CMOS image sensor with 3-stage cyclic-based analog-to-digital converters,” in 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.126–128, 2016.
    [22]
    T. Lyu, S. Y. Yao, K. M. Nie, et al., “A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors,” Sensors, vol. 14, no. 11, pp. 21603–21625, 2014. doi: 10.3390/s141121603
    [23]
    J. Lee, H. Park, B. Song, et al., “High frame-rate VGA CMOS image sensor using non-memory capacitor two-step single-slope ADCs,” IEEE Transactions on Circuits and Systems I:Regular Papers, vol. 62, no. 9, pp. 2147–2155, 2015. doi: 10.1109/TCSI.2015.2451791
    [24]
    J. W. Wei, X. Li, L. Sun, et al., “A low-power column-parallel gain-adaptive single-slope ADC for CMOS image sensors,” Electronics, vol. 9, no. 5, article no. 757, 2020. doi: 10.3390/electronics9050757
    [25]
    K. Imai, K. Yasutomi, K. Kagawa, et al., “A distributed ramp signal generator of column-parallel single-slope ADCs for CMOS image sensors,” IEICE Electronics Express, vol. 9, no. 24, pp. 1893–1899, 2012. doi: 10.1587/elex.9.1893
    [26]
    W. Saito, Y. Iizuka, N. Kato, et al., “A low noise and linearity improvement CMOS image sensor for surveillance camera with skew-relaxation local multiply circuit and on-chip testable ramp generator,” in 2021 IEEE Asian Solid-State Circuits Conference, Busan, Korea, pp.1–3, 2021.
    [27]
    S. Khan, S. Azeemuddin, and M. A. Sohel, “High-speed CMOS ramp generator using proteretic comparator,” in 2021 IEEE Asia Pacific Conference on Circuit and Systems, Penang, Malaysia, pp.5–8, 2021.
    [28]
    J. T. Xu, J. Yu, F. J. Huang, et al., “A 10-bit column-parallel single slope ADC based on two-step TDC with error calibration for CMOS image sensors,” Journal of Circuits, Systems and Computers, vol. 24, no. 4, article no. 1550054, 2015. doi: 10.1142/S0218126615500541
    [29]
    M. Padash and M. Yargholi, “Positive and negative feedback for linearity improvement and PVT compensation of the ramp generator,” Journal of Circuits, Systems and Computers, vol. 28, no. 2, article no. 1950028, 2019. doi: 10.1142/S0218126619500282
    [30]
    N. Lyu, N. M. Yu, and H. J. Zhang, “A high-speed column-parallel time-digital single-slope ADC for CMOS image sensors,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E99.A, no. 2, pp. 555–559, 2016. doi: 10.1587/transfun.E99.A.555
    [31]
    M. Padash and M. Yargholi, “A novel time-interleaved two-step single-slope ADC architecture based on both resistor ladder and current source ramp generator,” Microelectronics Journal, vol. 61, pp. 67–78, 2017. doi: 10.1016/j.mejo.2017.01.005
    [32]
    S. Naraghi, M. Courcy, and M. P. Flynn, “A 9-bit, 14 μw and 0.06 mm2 pulse position modulation ADC in 90 nm digital CMOS,” IEEE Journal of Solid-State Circuits, vol. 45, no. 9, pp. 1870–1880, 2010. doi: 10.1109/JSSC.2010.2050945
    [33]
    S. Sordo-Ibáñez, S. Espejo-Meana, B. Piñero-García, et al., “Four-channel self-compensating single-slope ADC for space environments,” Electronics Letters, vol. 50, no. 8, pp. 579–581, 2014. doi: 10.1049/el.2014.0664
  • 加载中

Catalog

    通讯作者: 陈斌, bchen63@163.com
    • 1. 

      沈阳化工大学材料科学与工程学院 沈阳 110142

    1. 本站搜索
    2. 百度学术搜索
    3. 万方数据库搜索
    4. CNKI搜索

    Figures(15)  / Tables(1)

    Article Metrics

    Article views (210) PDF downloads(21) Cited by()
    Proportional views
    Related

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return