Realization of Complete Boolean Logic and Combinational Logic Functionalities on A Memristor-based Universal Logic Circuit

LIAN Xiaojuan; SUN Chuanyang; TAO Zeheng; WAN Xiang; LIU Xiaoyan; CAI Zhikuang; WANG Lei

doi:10.23919/cje.2023.00.091

Article Contents

Article Navigation > Chinese Journal of Electronics > 2024 > Corrected proof

Xiaojuan LIAN, Chuanyang SUN, Zeheng TAO, et al., “Realization of Complete Boolean Logic and Combinational Logic Functionalities on A Memristor-based Universal Logic Circuit,” Chinese Journal of Electronics, vol. 33, no. 4, pp. 1–10, 2024 doi: 10.23919/cje.2023.00.091

Citation:

Xiaojuan LIAN, Chuanyang SUN, Zeheng TAO, et al., “Realization of Complete Boolean Logic and Combinational Logic Functionalities on A Memristor-based Universal Logic Circuit,” Chinese Journal of Electronics, vol. 33, no. 4, pp. 1–10, 2024 doi: 10.23919/cje.2023.00.091

Citation:

PDF( 10854 KB)

Realization of Complete Boolean Logic and Combinational Logic Functionalities on A Memristor-based Universal Logic Circuit

doi: 10.23919/cje.2023.00.091

1.
The College of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210023, China

More Information

Author Bio:
Xiaojuan LIAN Lian Xiaojuan got her B.S. degree in Electronic Science and Technology and the M.S. degree in Physical Electronics from Xidian University in 2008 and 2011 respectively. She received her Ph.D. degree in Electrical Engineering from the Universitat Autònoma de Barcelona, Spain, in 2014. She is currently an associate professor at the College of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications. Her research interests include memristive devices (RRAM, PCRAM and so on), information storage technology, and neuromorphic computing applications

Chuanyang SUN Sun Chuanyang received the B. E. degree in Electronic Information Engineering from Bengbu College, Anhui, China, in 2021. He currently pursuing for a master’s degree in Nanjing University of Posts and Telecommunications, engaged in the research of memory-computing integration based on memristor

Zeheng TAO Tao Zeheng received the B. E. degree in Electronic Science and Technology from Hunan University of Technology, Hunan, China, in 2021. He is currently working towards a master’s degree at Nanjing University of Posts and Telecommunications, focusing on research related to the integration of memory and computing using memristors

Xiang WAN Wan Xiang got his B.S. degree in Applied Physics and his M.S. degree in Materials Engineering from University of Science and Technology of China in 2011 and 2014 respectively. He received his Ph.D. degree in Electronic Science and Technology from Nanjing University in 2017. From 2019 to 2021, he held the postdoc position at the National Institute for Materials Science. He is currently a lecturer at the College of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications. His current research interests are the design, fabrication and modeling of electronic devices and systems for neuromorphic computation

Xiaoyan LIU received her Ph.D. degree in Microelectronics and Solid-Sate Electronics from Fudan University in 2019. She is currently an associate professor in Nanjing University of Posts and Telecommunications, workings on the researches mainly include the micro-LED array devices for visible light communication in free-space and underwater, memeristive devices for neuromorphic computing and artificial synapse

Zhikuang CAI Cai Zhikuang got his B.S. degree in Information Engineering from Nanjing University of Posts and Telecommunications in 2005. He received the Ph.D. degree from ASIC System Center at Southeast University in 2014. He is currently a professor at the College of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications. His research direction is low power SoC design and test, and Chiplet package and test

Lei WANG Wang Lei got his B.S. degree in Electrical Engineering from the Beijing University of Science and Technology in 2003, the M.S. degree in Electronic Instrumentation Systems from the University of Manchester in 2004, and the Ph.D. degree in 2009 at the University of Exeter. Between 2008 and 2011, he was employed as a Postdoctoral Research Fellow in the University of Exeter to work on a fellowship funded by European Commission. In 2020, he joined the Nanjing University of Posts and Telecommunications as a full Professor. His research interests include phase-change memories, neural networks, and other phase-change based optoelectronic devices and their potential applications
Corresponding author: Email: leiwang1980@njupt.edu.cn
Received Date: 2023-03-24
Accepted Date: 2023-11-13

Available Online: 2024-02-22

Abstract

Abstract

Memristors are a promising solution for building an advanced computing system due to their excellent characteristics, including small energy consumption, high integration density, fast write/read speed, great endurance and so on. In this work, we firstly design three basis logic XNOR1, XNOR2 and XOR gates by virtue of memristor ratioed logic (MRL), and further construct 1-bit numerical comparators, 2-bit numerical comparators and full adder 1 based on the above XNOR1, XNOR2 and XOR gates. Furthermore, we propose and design a universal logic circuit that can realize four different kinds of logic functions (AND, OR, XOR, XNOR) at the same time. Subsequently, a full adder 2 is built using XOR function of this universal logic circuit. Compared with the traditional CMOS circuits, the universal logic circuit designed in this work exhibits several merits such as fewer components, less power, and lower delay. This work demonstrates that memristors can be used as a potential solution for building a novel computing architecture.
- Memristor,
- universal logic circuit,
- MRL,
- numerical comparator,
- full adder

FullText(HTML)

References(40)

References

[1]	A. Nasrudin, A. F. Adzmi, and W. F. Hanim, “Nanoelectronics implementation of full adder with memristors,” in IEEE International Conference on Control System, Computing and Engineering, Penang, Malaysia, pp. 313–316, 2011.
[2]	N. Z. Haron and S. Hamdioui, “Why is CMOS scaling coming to an END?,” in 2008 3rd International Design and Test Workshop, Monastir, Tunisia, pp. 98–103, 2008.
[3]	A. A. Chien and V. Karamcheti, “Moore’s law: The first ending and a new beginning,” Computer, vol. 46, no. 12, pp. 48–53, 2013. doi: 10.1109/MC.2013.431
[4]	E. Ben-Sasson, A. Chiesa, E. Tromer, et al., “Succinct non-interactive zero knowledge for a von Neumann architecture,” in Proceedings of the 23rd USENIX Conference on Security Symposium, San Diego, CA, USA, pp. 781–796, 2014.
[5]	L. Dai, H. Guo, Q. P. Lin, et al., “An in-memory-computing design of multiplier based on multilevel-cell of resistance switching random access memory,” Chinese Journal of Electronics, vol. 27, no. 6, pp. 1151–1157, 2018. doi: 10.1049/cje.2018.08.006
[6]	M. S. Abdelouahab, R. Lozi, and L. Chua, “Memfractance: A mathematical paradigm for circuit elements with memory,” International Journal of Bifurcation and Chaos, vol. 24, no. 9, article no. 1430023, 2014. doi: 10.1142/S0218127414300237
[7]	D. B. Strukov, G. S. Snider, D. R. Stewart, et al., “The missing memristor found,” Nature, vol. 453, no. 7191, pp. 80–83, 2008. doi: 10.1038/nature06932
[8]	R. W. Hartenstein, A. G. Hirschbiel, and M. Weber, “Xputers: An open family of non-von neumann architectures,” in Architektur Von Rechensystemen, Tagungsband, 11. ITG/GI-Fachtagung, Berlin, Germany, pp. 45–48, 1990.
[9]	J. Borghetti, G. S. Snider, P. J. Kuekes, et al., “Memristive' switches enable ’stateful' logic operations via material implication,” Nature, vol. 464, no. 7290, pp. 873–876, 2010. doi: 10.1038/nature08940
[10]	J. G. Hu, D. M. Wang, and J. Wu, “A 2 kbits low power EEPROM for passive RFID tag IC,” Chinese Journal of Electronics, vol. 31, no. 1, pp. 18–24, 2022. doi: 10.1049/cje.2021.00.044
[11]	C. Li, D. Belkin, Y. N. Li, et al., “In-memory computing with memristor arrays,” in 2018 IEEE International Memory Workshop (IMW), Kyoto, Japan, pp. 1–4, 2018.
[12]	I. Vourkas and G. C. Sirakoulis, “Emerging memristor-based logic circuit design approaches: A review,” IEEE Circuits and Systems Magazine, vol. 16, no. 3, pp. 15–30, 2016. doi: 10.1109/MCAS.2016.2583673
[13]	M. H. Zou, J. L. Zhou, J. Sun, et al., “Improving efficiency and lifetime of logic-in-memory by combining IMPLY and MAGIC families,” Journal of Systems Architecture, vol. 119 article no. 102232, 2021. doi: 10.1016/j.sysarc.2021.102232
[14]	H. C. Long, J. T. Diao, X. Zhu, et al., “Logic implementation based on double memristors,” in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, pp. 1–5, 2021.
[15]	A. Chakraborty, P. S. Gupta, R. Singh, et al., “BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC),” Integration, vol. 81 pp. 254–267, 2021. doi: 10.1016/j.vlsi.2021.08.002
[16]	A. Chakraborty, V. Saurabh, P. S. Gupta, et al., “In-memory designing of Delay and Toggle flip-flops utilizing Memristor Aided loGIC (MAGIC),” Integration, vol. 66 pp. 24–34, 2019. doi: 10.1016/j.vlsi.2018.12.005
[17]	L. Guckert and E. E. Swartzlander, “MAD gates—Memristor logic design using driver circuitry,” IEEE Transactions on Circuits and Systems II:Express Briefs, vol. 64, no. 2, pp. 171–175, 2017. doi: 10.1109/TCSII.2016.2551554
[18]	S. Kvatinsky, N. Wald, G. Satat, et al., “MRL — memristor ratioed logic,” in 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, Turin, Italy, pp. 1–6, 2012.
[19]	A. S. Emara, A. H. Madian, H. H. Amer, et al., “Testing of memristor ratioed logic (MRL) XOR gate,” in 2016 28th International Conference on Microelectronics (ICM), Giza, Egypt, pp. 181–184, 2016.
[20]	Y. Q. Cui, W. W. Shan, W. T. Dai, et al., “An improved path delay variability model via multi-level fan-out-of-4 metric for wide-voltage-range digital CMOS circuits,” Chinese Journal of Electronics, vol. 32, no. 2, pp. 375–388, 2023. doi: 10.23919/cje.2021.00.447
[21]	S. Kvatinsky, G. Satat, N. Wald, et al., “Memristor-based material implication (IMPLY) logic: Design principles and methodologies,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 10, pp. 2054–2066, 2014. doi: 10.1109/TVLSI.2013.2282132
[22]	J. W. Sun, L. H. Zhao, S. P, Wen, et al., “Memristor-based neural network circuit of emotional habituation with contextual dependency,” IEEE Internet of Things Journal, vol. 10, no. 19, pp. 17382–17391, 2023. doi: 10.1109/JIOT.2023.3274116
[23]	J. W. Sun, Y. Y, Wang, P. Liu, et al., “Memristor-based neural network circuit with multimode generalization and differentiation on pavlov associative memory,” IEEE Transactions on Cybernetics, vol. 53, no. 5, pp. 3351–3362, 2023. doi: 10.1109/TCYB.2022.3200751
[24]	J. W. Sun, Y. Y. Wang, P. Liu, et al., “Memristor-based circuit design of PAD emotional space and its application in mood congruity,” IEEE Internet of Things Journal, vol. 10, no. 18, pp. 16332–16342, 2023. doi: 10.1109/JIOT.2023.3267778
[25]	R. S. Williams, “How we found the missing memristor,” IEEE Spectrum, vol. 45, no. 12, pp. 28–35, 2008. doi: 10.1109/MSPEC.2008.4687366
[26]	A. A. Garcia and L. O. Reyes, “Analysis and parameter extraction of memristive structures based on Strukov’s non-linear model,” Journal of Semiconductors, vol. 39, no. 12, article no. 124009, 2018. doi: 10.1088/1674-4926/39/12/124009
[27]	J. Mathew, R. S. Chakraborty, D. P. Sahoo, et al., “A novel memristor based physically unclonable function,” Integration, the VLSI Journal, vol. 51 pp. 37–45, 2015. doi: 10.1016/j.vlsi.2015.05.005
[28]	M. Khalid, S. Mukhtar, M. J. Siddique, et al., “Memristor based full adder circuit for better performance,” Transactions on Electrical and Electronic Materials, vol. 20, no. 5, pp. 403–410, 2019. doi: 10.1007/s42341-019-00135-5
[29]	X. Y. Xu, X. L. Cui, M. Y. Luo, et al., “Design of hybrid memristor-MOS XOR and XNOR logic gates,” in 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, China, pp. 1–2, 2017.
[30]	A. Singh, “Memristor based XNOR for high speed area efficient 1-bit full adder,” in 2017 International Conference on Computing, Communication and Automation (ICCCA), Greater Noida, India, pp. 1549–1553, 2017.
[31]	Y. Wu, H. Li, and Z. P. Zhang, “First demonstration of RRAM patterned by block copolymer self-assembly,” in 2013 IEEE International Electron Devices Meeting, Washington, DC, USA, pp. 20.8. 1–20.8. 4, 2013.
[32]	S. S. Dawley and P. A. Gajbhiye, “Design and comparative analysis of binary and quaternary logic circuits,” in 2016 World Conference on Futuristic Trends in Research and Innovation for Social Welfare (Startup Conclave), Coimbatore, India, pp. 1–6, 2016.
[33]	C. H. Huang and J. S. Wang, “High-performance and power-efficient CMOS comparators,” IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 254–262, 2003. doi: 10.1109/JSSC.2002.807409
[34]	A. A. Khatibzadeh and K. Raahemifar, “A study and comparison of full adder cells based on the standard static CMOS logic,” in Canadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat. No. 04CH37513), Niagara Falls, ON, Canada, pp. 2139–2142, 2004.
[35]	G. Z. Liu, S. H. Shen, P. P. Jin, et al., “Design of memristor-based combinational logic circuits,” Circuits, Systems, and Signal Processing, vol. 40, no. 12, pp. 5825–5846, 2021. doi: 10.1007/s00034-021-01770-1
[36]	X. P. Wang, R. Yang, Q. Chen, et al., “An improved memristor-CMOS XOR logic gate and a novel full adder,” in 2017 Ninth International Conference on Advanced Computational Intelligence (ICACI), Doha, Qatar, pp. 7–11, 2017.
[37]	S. H. Amer, A. H. Madian, and A. S. Emara, “Design and analysis of memristor-based min-max circuit,” in 2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Cairo, Egypt, pp. 187–190, 2015.
[38]	S. Mandal, J. Sinha, and A. Chakraborty, “Design of Memristor – CMOS based logic gates and logic circuits,” in 2019 2nd International Conference on Innovations in Electronics, Signal Processing and Communication (IESC), Shillong, India, pp. 215–220, 2019.
[39]	S. Panda, A. Banerjee, B. Maji, et al., “Power and delay comparison in between different types of full adder circuits,” International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, vol. 1, no. 3, pp. 168–172, 2012.
[40]	A. Singh, “Design and analysis of memristor-based combinational circuits,” IETE Journal of Research, vol. 66, no. 2, pp. 182–191, 2020. doi: 10.1080/03772063.2018.1486741