ZHANG Wei, ZHANG Liang, ZHANG Xu, MA Xuepo, LIU Yanyan. An Improved Current Mode Logic Latch[J]. Chinese Journal of Electronics, 2013, 22(1): 214-218.
Citation: ZHANG Wei, ZHANG Liang, ZHANG Xu, MA Xuepo, LIU Yanyan. An Improved Current Mode Logic Latch[J]. Chinese Journal of Electronics, 2013, 22(1): 214-218.

An Improved Current Mode Logic Latch

Funds:  This work is supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China (No.2012ZX03004008) and the Fundamental Research Funds for the Central Universities.
  • Received Date: 2011-08-01
  • Rev Recd Date: 2012-05-01
  • Publish Date: 2013-01-05
  • In order to reduce power consumption and additional chip area, an improved Current mode logic (CML) latch, which can work at a lower power supply without the level shifter, is presented. To compensate the speed loss caused by large voltage swing, a cross coupled pair is added to the load of the latch. A simplified model which divides operating situation into different phases is built to illustrate the operating principle of the structure and optimize the speed of the circuit. Further analysis also indicates that the latch can work at a much lower voltage supply. The proposed divider has been used in a frequency synthesizer. Measurements were made to support above features. It has been proved that the structure in this work has more advantages than the conventional ones.
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