HSRDN: High-Speed Router Design for Various NoC Topologies

E. Lakshmi Prasad; M. N. Giri Prasad; A. R. Reddy

doi:10.1049/cje.2020.01.005

Volume 29 Issue 2

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E. Lakshmi Prasad, M. N. Giri Prasad, A. R. Reddy, “HSRDN: High-Speed Router Design for Various NoC Topologies,” Chinese Journal of Electronics, vol. 29, no. 2, pp. 281-290, 2020, doi: 10.1049/cje.2020.01.005

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E. Lakshmi Prasad, M. N. Giri Prasad, A. R. Reddy, “HSRDN: High-Speed Router Design for Various NoC Topologies,” Chinese Journal of Electronics, vol. 29, no. 2, pp. 281-290, 2020, doi: 10.1049/cje.2020.01.005

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HSRDN: High-Speed Router Design for Various NoC Topologies

doi: 10.1049/cje.2020.01.005

1.
Department of ECE, JNTUACE, Anantapuramu, (AP)-515002, India;
2.
Department of RRC, MITS, Madanapalle, (AP)-517325, India

Funds: This work is supported by the MITS (RRC, JNTUA) on behalf of TEQIP-II World Bank Organization.

Received Date: 2017-07-27
Rev Recd Date: 2018-08-19
Publish Date: 2020-03-10

Abstract

Abstract

High-speed router design for network on chip (HSRDN) is proposed for controlling the traffic congestion and deadlocks. Diagonal based nearest-path routing algorithm for NoC (DNRAN) can mitigate the effect of latency by opting for the nearest-path to reach the destination in a network and HSRDN is part of DNRAN. When we analyze the performance of DNRAN for all proposed topologies, nearly 50% better in terms of latency reduction and high throughput over existing router architectures. The proposed topologies (2D-mesh, 2D-Star mesh over regional mesh (SMoRM), 3D-mesh, and 3D-torus) are tested with various applications, viz, audio, video and so on. Here, we also tested with cryptography application for DNRAN. When we analyzed the performance of experimental results, exclusively in 2D-SMoRM nearly 0.6 times latency get reduced, area expanded by 0.25 and 0.33 times throughput increase in 2D-SMoRM compared with 3D-mesh and 3D-torus. Therefore, DNRAN showed an exclusive performance in 2D-SMoRM compared with other two topologies.
- Logic Network on chip(NoC),
- Virtual channels,
- Latency,
- Congestion,
- Shortest path routing algorithm,
- 3D-mesh,
- 3D-torus

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References(18)

References

Anh T. Tran and Bevan M. Baas, “Achieving highperformance on-chip networks with shared buffer routers”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.22, No.6, pp.1391-1403, June 2014.

W. Dally and B. Towles, “Route packets, not wires: On-chip interconnection networks”, Proc. Design Automation Conf. (DAC), pp.683-689, 2001.

T. Moscibroda and O. Mutlu, “A case for bufferless routing in on-chip networks”, in Proc. ISCA, pp.196-207, Jun. 2009.

Mehdi Modarressi, Arash Tavakkol and Hamid SarbaziAzad, “Virtual point-to-point connections for nocs”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol.29, No.6, JUNE 2010.

E. Lakshmi Prasad, A.R. Reddy and M.N. Giri Prasad, “Efasbran: Error free adaptive shared buffer router architecture for network on chip”, ICCN 2016 Procedia Computer Science, Vol.89, pp.261-270, AUGUEST 2016.

En-Jui Chang, Hsien-Kai Hsin, ShuYen Lin, et al., “PathCongestion-aware adaptive routing with a contention prediction scheme for network-on-chip systems”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol.33, No.1, 2014.

Rabab Ezz-Eldin, Magdy A. El-Moursy and Hesham F. A. Hamed, “Process variation delay and congestion aware routing algorithm for asynchronous NoC design”, IEEE Transaction on Very Large Scale Integration Systems, Vol.24, No.3, pp.909-919, 2016.

Faizal Arya Samman, Thomas Hollstein and Manfred Glesner, “New theory for deadlock-free multicast routing in wormhole-switched virtualchannelless networks-on-chip”, IEEE Transaction on Parallel and Distributed Systems, Vol.22, No.4, pp.544-557, 2011.

Guoyue Jiang, Zhaolin Li, Fang Wang, et al., “A low-latency and low-power hybrid scheme for on-chip networks”, IEEE Transaction on Very Large Scale Integration Systems, Vol.23, No.4, 2015.

Mukund Rama krishna, Vamsi Krishna Kodati, Paul V. Gratz, et al., “Gca:Global congestion awareness for load balance in networks-on-chip”, IEEE Trans. on Parallel and Distributed Systems, Vol.27, No.7, pp.2022-2035, 2016.

R. S. Ramanujam, V. Soteriou, B. Lin, et al., “Extending the effective throughput of NoCs with distributed shared-buffer routers”, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., Vol.30, No.4, pp.548-561, 2011.

E. Lakshmi Prasad, A.R. Reddy and M.N. Giri Prasad “DVCR: Diagonal virtual channel NoC router architecture for multiprocessors”, Journal of Engineering and Applied Sciences, Vol.13, No.10, pp.3562-3566, 2018.

E. Lakshmi Prasad, A.R. Reddy and M.N. Giri Prasad, “Performance comparison of Network on chip Methods”, 2016 IEEE Online International Conference on Green Engineering and Technologies (IC-GET), 2017.

Abdul Quaiyum Ansari, Mohammad Rashid Ansari and Mohammad Ayoub Khan, “Modified quadrant-based routing algorithm for 3D torus network-on-chip architecture”, Perspectives in Science, Vol.8, pp.718-721, 2016.

Florentine Dubois, Abbas Sheibanyrad, Frederic Petrot, et al., “Elevator-First: A deadlock-free distributed routing algorithm for vertically partially connected 3D-NoCs”, IEEE Transaction on Computers, Vol.62, No.3, 2013.

A. E. Kiasari, Z. Lu and A. Jantsch, “An analytical latency model for networks on-chip”, IEEE Trans. Very Large Scale (VLSI) Syst., Vol.21, No.1, pp.113-123, 2013.

Umit Y. Ogras, Paul Bogdan and Radu Marculescu, “An analytical approach for network-on-chip performance analysis”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol.29, No.12, 2010.

M. P. Priyanka, E. Lakshmi Prasad and A. R. Reddy, “FPGA implementation of image encryption and decryption using AES 128-bit core” IEEE Int. Conf. on Communication and Electronics Systems (ICCES), pp.1-5, 2017.

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