E. Lakshmi Prasad, M. N. Giri Prasad, A. R. Reddy. HSRDN: High-Speed Router Design for Various NoC Topologies[J]. Chinese Journal of Electronics, 2020, 29(2): 281-290. doi: 10.1049/cje.2020.01.005
Citation: E. Lakshmi Prasad, M. N. Giri Prasad, A. R. Reddy. HSRDN: High-Speed Router Design for Various NoC Topologies[J]. Chinese Journal of Electronics, 2020, 29(2): 281-290. doi: 10.1049/cje.2020.01.005

HSRDN: High-Speed Router Design for Various NoC Topologies

doi: 10.1049/cje.2020.01.005
Funds:  This work is supported by the MITS (RRC, JNTUA) on behalf of TEQIP-II World Bank Organization.
  • Received Date: 2017-07-27
  • Rev Recd Date: 2018-08-19
  • Publish Date: 2020-03-10
  • High-speed router design for network on chip (HSRDN) is proposed for controlling the traffic congestion and deadlocks. Diagonal based nearest-path routing algorithm for NoC (DNRAN) can mitigate the effect of latency by opting for the nearest-path to reach the destination in a network and HSRDN is part of DNRAN. When we analyze the performance of DNRAN for all proposed topologies, nearly 50% better in terms of latency reduction and high throughput over existing router architectures. The proposed topologies (2D-mesh, 2D-Star mesh over regional mesh (SMoRM), 3D-mesh, and 3D-torus) are tested with various applications, viz, audio, video and so on. Here, we also tested with cryptography application for DNRAN. When we analyzed the performance of experimental results, exclusively in 2D-SMoRM nearly 0.6 times latency get reduced, area expanded by 0.25 and 0.33 times throughput increase in 2D-SMoRM compared with 3D-mesh and 3D-torus. Therefore, DNRAN showed an exclusive performance in 2D-SMoRM compared with other two topologies.
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