A 16-bit Hybrid ADC with Circular-Adder-Based Counting for 15μm Pitch 640×512 LWIR FPAs

HUANG Zhaofeng; ZHU Yajun; LU Wengao; NIU Yuze; ZHANG Shengdong; CHEN Zhongjian

doi:10.1049/cje.2020.01.006

Volume 29 Issue 2

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Article Navigation > Chinese Journal of Electronics > 2020 > 29(2): 291-296

HUANG Zhaofeng, ZHU Yajun, LU Wengao, et al., “A 16-bit Hybrid ADC with Circular-Adder-Based Counting for 15μm Pitch 640×512 LWIR FPAs,” Chinese Journal of Electronics, vol. 29, no. 2, pp. 291-296, 2020, doi: 10.1049/cje.2020.01.006

Citation:

HUANG Zhaofeng, ZHU Yajun, LU Wengao, et al., “A 16-bit Hybrid ADC with Circular-Adder-Based Counting for 15μm Pitch 640×512 LWIR FPAs,” Chinese Journal of Electronics, vol. 29, no. 2, pp. 291-296, 2020, doi: 10.1049/cje.2020.01.006

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A 16-bit Hybrid ADC with Circular-Adder-Based Counting for 15μm Pitch 640×512 LWIR FPAs

doi: 10.1049/cje.2020.01.006

1.
School of Electronic and Computer Engineering, Peking University, Shenzhen 518055, China;
2.
Department of Microelectronics, Peking University, Beijing 100871, China

Funds: This work is supported by the National Natural Science Foundation of China (No.61475009).

More Information

Corresponding author: LU Wengao (corresponding author) was born in Yuyao, China, in1978. He received the B.S. and Ph.D. degrees in electrical engineering from Peking University, China, in 2000 and 2005, respectively. In 2005, he joined the Department of Microelectronics, Peking University, as an assistant professor, where he has been an associate professor since 2008. His research interests include low-noise interface ASICs for sensors, ADCs, and power management ICs. (Email:wglu@pku.edu.cn)
Received Date: 2019-02-11
Rev Recd Date: 2019-04-19
Publish Date: 2020-03-10

Abstract

Abstract

A hybrid Analog to digital converter (ADC) is presented for long-wave infrared focal plane arrays. A two-stage quantization structure is applied in the folding integration process, which results in better chargehandling capacity and higher linearity compared with conventional designs while using fewer transistors at the pixel level. By employing a circular-adder-based counting structure with 3T dynamic memory cells, hardware consumption can be reduced. A pixel circuit of pitch 15μm has been designed using the 0.18μm Complementary metal-oxide-semiconductor (CMOS) process. The power consumption of the pixel-level ADC is 0.214μW, and the charge-handling capacity is 1Ge-. Simulation results demonstrate a signal-to-noise ratio of 90dB and a nonlinearity of 0.11%.
- Infrared focal plane arrays (IRFPAs),
- Readout integrated circuit,
- Hybrid ADC,
- 3T memory,
- Folding integration

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References(17)

References

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