WANG Ke, FAN Chaojie, PAN Wenjie, ZHOU Jianjun. Nonlinearity Calibration for Pipelined ADCs by Splitting Capacitors with Self-Tracking Comparator Thresholds[J]. Chinese Journal of Electronics, 2015, 24(3): 474-479. doi: 10.1049/cje.2015.07.006
Citation: WANG Ke, FAN Chaojie, PAN Wenjie, ZHOU Jianjun. Nonlinearity Calibration for Pipelined ADCs by Splitting Capacitors with Self-Tracking Comparator Thresholds[J]. Chinese Journal of Electronics, 2015, 24(3): 474-479. doi: 10.1049/cje.2015.07.006

Nonlinearity Calibration for Pipelined ADCs by Splitting Capacitors with Self-Tracking Comparator Thresholds

doi: 10.1049/cje.2015.07.006
Funds:  This work is supported by the Integrated Circuits Program from Shanghai Science and Technology Committee (No.11511505000).
  • Received Date: 2014-09-01
  • Rev Recd Date: 2014-12-18
  • Publish Date: 2015-07-10
  • A digital background calibration technique which mainly corrects nonlinear errors of residue amplifiers in pipelined analog-to-digital converters (ADCs) is presented. The proposed technique extracts the nonlinear errors by splitting sampling capacitors and inserting two extra comparators, and is highly effective as long as the input signal is busy. The method of self-tracking comparator thresholds is proposed to reduce the time of convergence with low complexity for any bit cases in a pipelined ADC. Both measurement and correction are processed in digital domain. After calibration, the behavioral simulation shows that the Signal-to-noise-and-distortion ratio (SNDR) is raised from 55.4dB to 90.2dB and the Spurious-free dynamic range (SFDR) is improved from 61.6dB to 102dB in a 16-bit prototype pipelined ADC with 0.5% capacitor mismatches and 4.5% gain compression of the residue amplifier.
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