ZHONG Yinghui, ZANG Huaping, WANG Haili, SUN Shuxiang, LI Kaikai, DING Peng, JIN Zhi. T-Gate Fabrication of InP-Based HEMTs Using PMGI/ZEP520A/PMGI/ZEP520A Stacked Resist[J]. Chinese Journal of Electronics, 2016, 25(3): 448-452. doi: 10.1049/cje.2016.05.009
Citation: ZHONG Yinghui, ZANG Huaping, WANG Haili, SUN Shuxiang, LI Kaikai, DING Peng, JIN Zhi. T-Gate Fabrication of InP-Based HEMTs Using PMGI/ZEP520A/PMGI/ZEP520A Stacked Resist[J]. Chinese Journal of Electronics, 2016, 25(3): 448-452. doi: 10.1049/cje.2016.05.009

T-Gate Fabrication of InP-Based HEMTs Using PMGI/ZEP520A/PMGI/ZEP520A Stacked Resist

doi: 10.1049/cje.2016.05.009
Funds:  This work is supported by the National Natural Science Foundation of China (No.61404115, No.61434006) and the Postdoctoral Science Foundation of Henan Province (No.2014006).
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  • Corresponding author: JIN Zhi received the Ph.D. degree in electronic engineering from China University of Jilin. He is now a professor in the Institute of Microelectronics, Chinese Academy of Sciences, China. His research interests include InPbased devices fabrication, graphene transistor fabrication, THz devices fabrication, design of ultra high-speed circuits. (Email: jinzhi@ime.ac.cn)
  • Received Date: 2015-10-08
  • Rev Recd Date: 2015-12-15
  • Publish Date: 2016-05-10
  • PMGI/ZEP520A/PMGI/ZEP520A fourlayer resist stack is firstly proposed for T-gates fabrication of InP-based High electron mobility transistors (HEMTs). Gate-head and gate-foot are exposed in single-step Electron beam lithography (EBL), which avoids alignment deviation by automatic self-alignment. The newly introduced PMGI at the bottom greatly improves the adhesiveness of ZEP520A resist with the substrate. The optimal gate-foot length reaches 101nm for a design of 50nm gate footprint pattern, and which can be improved to be 66.8nm for 30nm gate footprint pattern. Finally, Tgates in nanometer regime have been successfully incorporated into InP-based HEMTs fabrication. Benefiting from both the narrow gate-foot and the reduced parasitic gatecapacitance by single-step EBL technique with the fourlayer resist stack, the fabricated devices with gate-foot length of 101nm demonstrate excellent DC and RF performances: the maximum extrinsic transconductance, the current-gain cutoff frequency and maximum oscillation frequency are 1051mS/mm, 249GHz and 415GHz, respectively.
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