ZHOU Fang, WU Ning, ZHANG Xiaoqiang, ZHOU Lei, YE Yunfei. An Energy-Aware Voltage-Frequency Island Partition Method for NoC[J]. Chinese Journal of Electronics, 2016, 25(3): 453-459. doi: 10.1049/cje.2016.05.010
Citation: ZHOU Fang, WU Ning, ZHANG Xiaoqiang, ZHOU Lei, YE Yunfei. An Energy-Aware Voltage-Frequency Island Partition Method for NoC[J]. Chinese Journal of Electronics, 2016, 25(3): 453-459. doi: 10.1049/cje.2016.05.010

An Energy-Aware Voltage-Frequency Island Partition Method for NoC

doi: 10.1049/cje.2016.05.010
Funds:  This work is supported by the Natural Science Foundation of China (No.61376025), the Industry-academic Joint Technological Innovations Fund Project of Jiangsu (No.BY2013003-11), the Funding of Jiangsu Innovation Program for Graduate Education (No. KYLX 0273) and the Fundamental Research Funds for the Central Universities.
  • Received Date: 2014-09-09
  • Rev Recd Date: 2015-03-23
  • Publish Date: 2016-05-10
  • To deal with the issues of energy consumption for Network on chip (NoC), this paper proposes a method for partitioning an NoC architecture into multiple voltage-frequency islands to achieve low energy consumption. The method considers the number of Voltagefrequency islands (VFIs), delay and reliability as multiconstraints. A mathematical model for Integer linear program (ILP) algorithm is constructed and LPSolve is used to solve the issues of VFI partition. The validity of the VFI partition method is accurately verified for E3S and MMS. Simulation results show that the proposed method is more reasonable and smaller consumption can be a chieved while multi-constraints are met. This method can get less energy consumption from 33.6% to 9.1% or 16.7% than those by the other methods.
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  • M. Popovich, E.G. Friedman, M. Sotman and A. Kolodny, "Onchip power distribution grids with multiple supply voltages for high performance integrated circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.16, No.7, pp.908-921, 2008.
    Wan-Ping. Lee, H.Y. Liu and Yao-Wen Chang, "Voltage island aware floorplanning for power and timing optimization", Proc. of ICCAD, San Jose, CA, USA, pp.389-394, 2006.
    D. Sengupta and R.A. Saleh, "Application-driven voltage-island partitioning for low-power system-on-chip design", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.28, No.3, pp.316-326, 2009.
    Ghosh Pavel and Sen Arunabha, "Energy efficient mapping and voltage islanding for regular NoC under design constraints", International Journal of High Performance Systems Architecture, Vol.2, No.3-4, pp.132-144, 2010.
    U.Y. Ogras, R. Marculescu, D. Marculescu and Eun Gu Jung, "Design and management of voltage-frequency island partitioned networks-on-chip", IEEE Transactions on Very Large An Energy-Aware Voltage-Frequency Island Partition Method for NoC 459 Scale Integration (VLSI) Systems, Vol.17, No.3, pp.330-341, 2009.
    Zhang Jianxian, Zhou Duan and Yang Yin-tang, "Energy optimization of NoC based on voltage-frequency islands under processor reliability constraints", Journal of Electronics & Information Technology, Vol.33, No.9, pp.2205-2211, 2011. (in Chinese)
    Chang Zhengwei, Xiong Guangze and Sang Nan, "Energy-and reliability-aware mapping for NoC implemented with voltage islands", Journal of Computer-Aided Design & Computer Graphics, Vol.21, No.1, pp.19-26, 2009. (in Chinese)
    Liu Bin, Chang Zhenchao and Zhang Xingming, "Genetic algorithm based NoC voltage-frequency island partition method", Application Research of Computers, Vol.29, No.10, pp.3740- 3743, 2012. (in Chinese)
    Baoxian Zhao, H. Aydin and Dakai Zhu, "Reliability-aware dynamic voltage scaling for energy-constrained real-time embedded systems", Proc. of IEEE International Conf. Computer Design (ICCD), Squaw Creek, Lake Tahoe, CA, USA, pp.633-639, 2008.
    Xu Chao, He Yan-xiang and Chen Yong, "A task scheduling method to increase the reliability of the multicore system". Acta Electronica Sinica, Vol.41, No.5, pp.1019-1024, 2013. (in Chinese)
    Wang Bin, Wu Chunming, Yang Qiang, et al., "Dynamic reliability analysis model for fault-tolerant network routing", Chinese Journal of Electronics, Vol.21, No.3, pp.500-504, 2012.
    Wang Xiaoming and Yang Tao, "ERMR: Energy-efficient and Reliability-ensured multipath routing for WMSNs", Chinese Journal of Electronics, Vol.20, No.2, pp.329-332, 2012.
    Ge Fen, Wu Ning, Qin Xiao Lin, et al., "Network monitor based dynamic fault-tolerant routing for application-specific network on chip", Acta Electronica Sinica, Vol.41, No.11, pp.2135-2143, 2013. (in Chinese)
    Ge Fen and Wu Ning, "Genetic algorithm based mapping and routing approach for network on chip architectures", Chinese Journal of Electronics. Vol.19, No.1, pp.91-96, 2010.
    Lap-Fai Leung and Chi-ying Tsui, "Energy-aware synthesis of networks-on-chip implemented with voltage islands", Proc. of the 44th Annual Conference on Design Automation, San Diego, California, USA, pp.128-131, 2007.
    D. Zhu, R Melhem and D Mosse, "The effects of energy management on reliability in real-time embedded systems", Proc. of the International Conference on Computer Aided Design, San Jose, CA, USA, pp.35-40, 2004.
    R. Dick, "Embedded system synthesis benchmarks suite (E3S)", available at http://ziyang.eecs.umich.edu/~dickrp/e3s/, 2013- 6/2014-9.
    Jian-Jun Han, Man Lin, Dakai Zhu and Laurence T. Yang, "Contention-aware energy management scheme for NoC-based multicore real-time systems", IEEE Transactions on Parallel and Distributed Systems, Vol.26, No.3, pp.691-701, 2015.
    E. Seo, J. Jeong, S. Park and J. Lee, "Energy efficient scheduling of realtime tasks on multicore processors", IEEE Transactions on Parallel and Distributed Systems, Vol.19, No.11, pp.1540- 1552, 2008.
    A.B. Kahng, B. Li, L.-S. Peh and K. Samadi, "Orion 2.0: A fast and accurate NoC power and area model for early-stage design space exploration", Proc. of the Conf. on DATE, Nice, France, pp.423-428, 2009.
    David Rhodes and Robert Dick, "Task graphs for free (TGFF)", available at http://ziyang.eecs.umich.edu/~dickrp/tgff, 2008-4.
    Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen and Norman P. Jouppi, "McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures", Proc. of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, New York, USA, pp.469-480, 2009.
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