Cache Power Optimization Based on Compare-Based Adaptive Clock Gating and Its 65nm SoC Implementation

LI Jie; WAN Xing; WU Jianbing; SHAN Weiwei

doi:10.1049/cje.2016.06.029

Volume 26 Issue 1

Turn off MathJax

Article Contents

Article Navigation > Chinese Journal of Electronics > 2017 > 26(1): 128-131

LI Jie, WAN Xing, WU Jianbing, et al., “Cache Power Optimization Based on Compare-Based Adaptive Clock Gating and Its 65nm SoC Implementation,” Chinese Journal of Electronics, vol. 26, no. 1, pp. 128-131, 2017, doi: 10.1049/cje.2016.06.029

Citation:

LI Jie, WAN Xing, WU Jianbing, et al., “Cache Power Optimization Based on Compare-Based Adaptive Clock Gating and Its 65nm SoC Implementation,” Chinese Journal of Electronics, vol. 26, no. 1, pp. 128-131, 2017, doi: 10.1049/cje.2016.06.029

Citation:

PDF( 533 KB)

Cache Power Optimization Based on Compare-Based Adaptive Clock Gating and Its 65nm SoC Implementation

doi: 10.1049/cje.2016.06.029

National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China

Funds: This work is supported by National Natural Science Foundation of China (No.61574033, No.61550110244), National 863 project (No.2015AA016601), Qing Lan Project and Open Research Funding of State Key Laboratory of ASIC and System, Fudan University (No.2015KF010).

More Information

Corresponding author: SHAN Weiwei (corresponding author) was born in 1982. She received Ph.D. degree in microelectronics from Tsinghua University in 2009. She is currently an associate professor in Southeast University, China. Her research mainly focuses on low power integrated circuit design and information security.(Email:wwshan@seu.edu.cn)
Received Date: 2014-10-20
Rev Recd Date: 2015-02-13
Publish Date: 2017-01-10

Abstract

Abstract

In most embedded microprocessor based System on chips (SoCs), cache has become a major source of power consumption due to its increasing size and high access rate. Power optimization of cache based on Compare-based adaptive clock gating (CACG) is proposed to reduce the power waste due to cache idle. By detecting the cache's working state, the CACG can automatically turn off its clock when it is in idle state, saving a large percentage of dynamic power. Measurements of a real SoC chip fabricated under TSMC 65nm CMOS process show that an average of 30.3% power reduction is gained in Dhrystone test benchmark at a cost of negligible area overhead and no virtually performance loss.
- Self-adaptive clock gating,
- Embedded processor,
- Cache idle,
- Low power

FullText(HTML)

References(8)

References

Youhua Shi, Hiroaki Igarashi, Masao Yanagisawa, et al., "Suspicious timing error detection and recovery with in-cycle clock gating", Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), pp.335-340, 2013.

YS Shao and David Brooks, "Energy characterization and instruction-level energy model of Intel's Xeon Phi processor", Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pp.389-394, 2013.

Carazo, Pablo, Castro, et al., "L1 data cache power reduction using a forwarding predictor", Proceedings of the 20th International workshop on Power and Timing Modeling, Optimization, and Simulation, France, pp.116-125, 2010.

Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, et al., "An energyefficient floorplan driven high-level synthesis algorithm for multiple clock domains design", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp.1376-1391, 2015.

Chang X, Zhang M, Zhang G, et al., "Adaptive clock gating technique for low power IP core in SoC design", IEEE International Symposium on Circuits and Systems (ISCAS), pp.2120-2123, 2007.

Cheng Xu, Xiao-Yin Wang, Jun-Lin Lu, et al., "Research progress of UniCore CPUs and PKUnity SoCs", Journal of Computer Science and Technology, Vol.25 No.2, pp.200-213, 2010.

Tyler A. Simon, William A. Ward Jr and Alan P. Boss, "Performance analysis of Intel multiprocessors using astrophysics simulations", Concurrency and Computation:Practice and Experience, Vol.24 No.2, pp.155-166, 2012.

David Padua, "Benchmarks", Encyclopedia of Parallel Computing, Springer US, pp.127-129, 2011.

Relative Articles

Supplements(0)

Cited By

Proportional views