LI Jie, WAN Xing, WU Jianbing, SHAN Weiwei. Cache Power Optimization Based on Compare-Based Adaptive Clock Gating and Its 65nm SoC Implementation[J]. Chinese Journal of Electronics, 2017, 26(1): 128-131. doi: 10.1049/cje.2016.06.029
Citation: LI Jie, WAN Xing, WU Jianbing, SHAN Weiwei. Cache Power Optimization Based on Compare-Based Adaptive Clock Gating and Its 65nm SoC Implementation[J]. Chinese Journal of Electronics, 2017, 26(1): 128-131. doi: 10.1049/cje.2016.06.029

Cache Power Optimization Based on Compare-Based Adaptive Clock Gating and Its 65nm SoC Implementation

doi: 10.1049/cje.2016.06.029
Funds:  This work is supported by National Natural Science Foundation of China (No.61574033, No.61550110244), National 863 project (No.2015AA016601), Qing Lan Project and Open Research Funding of State Key Laboratory of ASIC and System, Fudan University (No.2015KF010).
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  • Corresponding author: SHAN Weiwei (corresponding author) was born in 1982. She received Ph.D. degree in microelectronics from Tsinghua University in 2009. She is currently an associate professor in Southeast University, China. Her research mainly focuses on low power integrated circuit design and information security.(Email:wwshan@seu.edu.cn)
  • Received Date: 2014-10-20
  • Rev Recd Date: 2015-02-13
  • Publish Date: 2017-01-10
  • In most embedded microprocessor based System on chips (SoCs), cache has become a major source of power consumption due to its increasing size and high access rate. Power optimization of cache based on Compare-based adaptive clock gating (CACG) is proposed to reduce the power waste due to cache idle. By detecting the cache's working state, the CACG can automatically turn off its clock when it is in idle state, saving a large percentage of dynamic power. Measurements of a real SoC chip fabricated under TSMC 65nm CMOS process show that an average of 30.3% power reduction is gained in Dhrystone test benchmark at a cost of negligible area overhead and no virtually performance loss.
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