An Encoder with Speed over 40Gbps for RC LDPC Codes with Rates Up to 0.96

HE Zhiyong; ZHAO Qiang; XU Hushan; CUI Wenjuan; LUO Yuxi

doi:10.1049/cje.2016.06.039

Volume 25 Issue 5

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HE Zhiyong, ZHAO Qiang, XU Hushan, CUI Wenjuan, LUO Yuxi. An Encoder with Speed over 40Gbps for RC LDPC Codes with Rates Up to 0.96[J]. Chinese Journal of Electronics, 2016, 25(5): 921-927. doi: 10.1049/cje.2016.06.039

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HE Zhiyong, ZHAO Qiang, XU Hushan, CUI Wenjuan, LUO Yuxi. An Encoder with Speed over 40Gbps for RC LDPC Codes with Rates Up to 0.96[J]. Chinese Journal of Electronics, 2016, 25(5): 921-927. doi: 10.1049/cje.2016.06.039

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An Encoder with Speed over 40Gbps for RC LDPC Codes with Rates Up to 0.96

doi: 10.1049/cje.2016.06.039

Institute of Modern Physics, Chinese Academy of Sciences, Lanzhou 730000, China

Received Date: 2014-07-29
Rev Recd Date: 2014-11-17
Publish Date: 2016-09-10

Abstract

Abstract

We propose a class of Rate-compatible (RC) Low-density parity-check (LDPC) codes with a very wide range of code rates. To widen the range of rates, we have developed an optimal transmission scheme to push the upper bound of code rates to 0.96. Characterized by a parity check matrix in a dual-diagonal form, the proposed RC LDPC code can be encoded in linear time. Constructed from shifted identity sub-matrices, the proposed codes are particularly well-suited for the high-speed implementation of parallel encoders. Furthermore, the encoder can be implemented efficiently with several left circular shifters and XOR gates. To maximize the encoding speed, we have proposed a q-parallel encoder architecture, where q is the size of each sub-matrix. The implementation results into Field programmable gate array (FPGA) devices indicate that a 72-parallel encoder for the proposed RC LDPC code with a code rate from 0.5 to 0.96 is capable of reaching a speed of 42 Gigabits per second (Gbps) using a clock frequency of 300MHz.
- Low-density parity-check codes (LDPC),
- High-speed encoder,
- Field programmable gate array (FPGA) implementation

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References(15)

References

J. Ha, J. Kim, D. Klinc, et al., "Rate-compatible punctured low-density parity-check codes with short block lengths", IEEE Trans. Info. Theory, Vol.52, No.2, pp.728-738, 2006.

H. Park, J.W. Kang, K.S. Kim, et al., "Efficient puncturing method for rate-compatible low-density parity-check codes", IEEE Trans. Wireless Commun., Vol.6, No.11, pp.3914-3919, 2007.

M. El-Khamy, J. Hou and N. Bhushan, "Design of ratecompatible structured LDPC codes for hybrid ARQ applications", IEEE J. Selec. Areas in Commun., Vol.27, No.6, pp.965-973, 2009.

Badri N. Vellambi and Faramarz Fekri, "Finite-length ratecompatible LDPC codes:A novel puncturing scheme", IEEE Trans. Communications, Vol.57, No.2, pp.297-302, 2009.

J. Kim, A. Ramamoorthy and S.W. McLaughlin, "The design of efficiently-encodable rate-compatible LDPC codes", IEEE Trans. Communications, Vol.57, No.2, pp.365-375, 2009.

R. Asvadi and A.H. Banihashemi, "A rate-compatible puncturing scheme for finite-length LDPC codes", IEEE Commun. Lett., Vol.17, No.1, pp.147-150, 2013.

ZHANG Guohua and WANG Xinmei, "Construction of lowdensity parity-check codes based on frequency-hopping sequences", Chinese Journal of Electronics, Vol.18, No.1, pp.141-144, 2009.

T. Richardson, M.A. Shokrohalli and R. Urbanke, "Design of capacity approaching irregular low density parity check codes", IEEE Trans. Inform. Theory, Vol.47, No.2, pp.619-637, 2001.

Z. He, S. Roy and P. Fortier, "Capacity-approaching LDPC codes with low error floors for high-speed digital communications", the 23rd Biennial Symposium on Communications, Kingston, Canada, pp.10-13, 2006.

M.P.C. Fossorier, "Quasi-cyclic low-density parity-check codes from circulant permutation matrices", IEEE Trans. Inform. Theory, Vol.50, No.8, pp.1788-1793, 2004.

Z. He, P. Fortier and S. Roy, "A class of irregular LDPC codes with low error floor and low encoding complexity", IEEE Commun. Lett., Vol.10, No.5, pp.372-374, 2006.

MA Kexiang, LI Yongzhao, ZHANG Hailin, et al., "A belief propagation algorithm with set-breaking to lower error-floors of low-density parity-check codes", Chinese Journal of Electronics, Vol.22, No.3, pp.604-608, 2013.

G.J. Han, X.C. Liu and Y. Gong, "Layered dynamic schedulings for BP decoding of LDPC codes over GF(q)", Chinese Journal of Electronics, Vol.22, No.3, pp.609-614, 2013.

Z. He, S. Roy and P. Fortier, "FPGA implementation of LDPC decoders based on joint row-column decoding algorithm", IEEE International Symposium on Circuits and Systems, pp.1653-1656, 2007.

Z. He, S. Roy and P. Fortier, "Lowering error floor of LDPC codes using joint row-column decoding algorithm", IEEE International Conferences on Communications, pp.920-925, 2007.

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