PENG Yuanxi, CHEN Jiyang, LEI Yuanwu, HE Tingting, DENG Ziye. Low-Latency SRT Division and Square Root Based on Remainder and Quotient Prediction[J]. Chinese Journal of Electronics, 2017, 26(1): 58-64. doi: 10.1049/cje.2016.10.024
Citation: PENG Yuanxi, CHEN Jiyang, LEI Yuanwu, HE Tingting, DENG Ziye. Low-Latency SRT Division and Square Root Based on Remainder and Quotient Prediction[J]. Chinese Journal of Electronics, 2017, 26(1): 58-64. doi: 10.1049/cje.2016.10.024

Low-Latency SRT Division and Square Root Based on Remainder and Quotient Prediction

doi: 10.1049/cje.2016.10.024
Funds:  This work is supported by Aerospace Science Fund of China (No.2013ZC88003), and National Natural Science Foundation of China (No.61402499).
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  • Corresponding author: CHEN Jiyang (corresponding author) received the B.S. degree and M.S. degree in computer science in 2012 and 2015, respectively, from National University of Defense and Technology, China. Her research interests include high performance computing, multi-core architectures and on-chip networks. (Email:824750961@qq.com)
  • Received Date: 2014-11-24
  • Rev Recd Date: 2015-05-17
  • Publish Date: 2017-01-10
  • Sweeney, Robertson and Tocher (SRT) algorithm is a common and efficient way for division and square root (div/sqrt). We present to overlap two iterations into one cycle by predicting remainder and quotient. To reduce latency, redundant representation is used superiorly, as well as the use of a minimum redundancy factor. Division and square root can be integrated into one unit which causes a reduction in hardware cost. With 40nm technology library, the area of our architecture after layout design, is 37795μm2, the power is 81.19mW and the delay is only 656ps. The cycles for double-precision division and square root are 17 and 16, respectively. Experiments show our architecture achieves small latency and high frequency, together with modest area and power.
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