Low Cost 1D DCT Core for Multiple Video Codec

JIA Rui; CHEN Rui; LIN Colin Yu; GUO Zhenhong; YANG Haigang

doi:10.1049/cje.2016.10.026

Volume 25 Issue 6

Turn off MathJax

Article Contents

Article Navigation > Chinese Journal of Electronics > 2016 > 25(6): 1052-1057

JIA Rui, CHEN Rui, LIN Colin Yu, et al., “Low Cost 1D DCT Core for Multiple Video Codec,” Chinese Journal of Electronics, vol. 25, no. 6, pp. 1052-1057, 2016, doi: 10.1049/cje.2016.10.026

Citation:

JIA Rui, CHEN Rui, LIN Colin Yu, et al., “Low Cost 1D DCT Core for Multiple Video Codec,” Chinese Journal of Electronics, vol. 25, no. 6, pp. 1052-1057, 2016, doi: 10.1049/cje.2016.10.026

JIA Rui, CHEN Rui, LIN Colin Yu, et al., “Low Cost 1D DCT Core for Multiple Video Codec,” Chinese Journal of Electronics, vol. 25, no. 6, pp. 1052-1057, 2016, doi: 10.1049/cje.2016.10.026

Citation:

JIA Rui, CHEN Rui, LIN Colin Yu, et al., “Low Cost 1D DCT Core for Multiple Video Codec,” Chinese Journal of Electronics, vol. 25, no. 6, pp. 1052-1057, 2016, doi: 10.1049/cje.2016.10.026

PDF( 1932 KB)

Low Cost 1D DCT Core for Multiple Video Codec

doi: 10.1049/cje.2016.10.026

1.
Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China;
2.
The University of Chinese Academy of Sciences, Beijing 100190, China

Funds: This work is supported by the National Natural Science Foundation of China (No.61271149, No.61106033, No.61204045).

Received Date: 2014-08-19
Rev Recd Date: 2015-01-22
Publish Date: 2016-11-10

Abstract

Abstract

The expandability of high demands for multimedia applications brings out more and more video standards for improving the coding and compression efficiency. As the most commonly used transform, Discrete cosine transform (DCT) achieves excellent energy compaction property and good compression efficiency. Hardware sharing is the mostly used efficient strategy to reduce the cost for video codec. Based on traditional matrix factorization, this paper makes three observations to direct the design of proposed hardware sharing architecture. The proposed architecture can be generally used to compute 8×8 DCT of AVS, H.264, VC-1 and HEVC in a low cost way, and can be used to decode Full-HD and WQXGA formate video sequences in real time. The design has been synthesized in 0.13 μm technology. The synthesis results show that the proposed architecture achieves 76.9% reduction in gate count, 85.6% decrease in power consumption and 35% improvement in operational speed in comparison with other existing designs.
- Discrete cosine transform (DCT),
- 8×,
- 8 integer transform,
- AVS,
- H.264,
- VC-1,
- HEVC,
- Hardware sharing

FullText(HTML)

References(22)

References

ITU-T Rec. H.264/ISO/IEC 14496-10 AVC, 2003.

Standard for Television, "VC-1 compressed video bitstream format and decoding process", SMPTE 421M, 2006.

L. Yu, S. Chen and J. Wang, "Overview of AVS-video coding standards", Signal processing: Image communication, Vol.24, No.4, pp.247-262, 2009.

G.J. Sullivan, J. Ohm, W.-J. Han and T. Wiegand, "Overview of the high efficiency video coding HEVC standard", IEEE Transactions on Circuits and Systems for Video Technology, Vol.22, No.12, pp.1649-1668, 2012.

C.-C. Ju, et al., "A full-HD 60fps AVS/H.264/VC-1/MPEG-2 video decoder for digital home applications", 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), IEEE, pp.1-4, 2011.

A. Ahmed, et al., "N point DCT VLSI architecture for emerging HEVC standard", VLSI Design, Vol.2012, pp.6, 2012.

H. Liang, H. Weifeng, et al., "A full-pipelined 2-d IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard", IEICE Electronics Express, Vol.10, No.9, pp.20130210-20130210, 2013.

M. Martuza and K.A. Wahid, "Implementation of a cost-shared transform architecture for multiple video codecs", Journal of Real-Time Image Processing, pp.1-12, 2012.

C.-P. Fan, C.-H. Fang, et al., "Fast multiple inverse transforms with low-cost hardware sharing design for multistandard video decoding", IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.58, No.8, pp.517-521, 2011.

Y.-C. Chao, S.-T. Wei,et al., "An efficient architecture of multiple 8×8 transforms for H.264/AVC and VC-1 decoders", 2010 International Conference on Green Circuits and Systems (ICGCS), pp.595-598, 2010.

H. Qi, Q. Huang and W. Gao, "A low-cost very large scale integration architecture for multistandard inverse transform", IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.57, No.7, pp.551-555, 2010.

G. Liu, "An area-efficient IDCT architecture for multiple video standards", 20102nd International Conference on Information Science and Engineering (ICISE), IEEE, pp.3518-3522, 2010.

C.-P. Fan and G.-A. Su, "Fast algorithm and low-cost hardwaresharing design of multiple integer transforms for VC-1", IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.56, No.10, pp.788-792, 2009.

Y. Li, Y. He and S. Mei, "A highly parallel joint VLSI architecture for transforms in H.264/AVC", Journal of Signal Processing Systems, Vol.50, No.1, pp.19-32, 2008.

G.-A. Su and C.-P. Fan, "Low-cost hardware-sharing architecture of fast 1-D inverse transforms for H.264/AVC and AVS applications", IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.55, No.12, pp.1249-1253, 2008.

C.-P. Fan and G.-A. Su, "Efficient low-cost sharing design of fast 1-D inverse integer transform algorithms for H.264/AVC and VC-1", Signal Processing Letters, IEEE, Vol.15, pp.926-929, 2008.

S. Lee and K. Cho, "Circuit implementation for transform and quantization operations of H.264/MPEG-4/VC-1 video decoder", Design & International Conference on Technology of Integrated Systems in Nanoscale Era, 2007. DTIS., IEEE, pp.102-107, 2007.

S. Lee and K. Cho, "Architecture of transform circuit for video decoder supporting multiple standards", Electronics Letters, Vol.44, No.4, pp.274-276, 2008.

S. Kim, H. Chang, S. Lee and K. Cho, "VLSI design to unify IDCT and IQ circuit for multistandard video decoder", Proceedings of the 200912th International Symposium on Integrated Circuits, ISIC'09., IEEE, pp.328-331, 2009.

K.A. Wahid, M. Martuza, M. Das and C. McCrosky, "Efficient hardware implementation of 8×8 integer cosine transforms for multiple video codecs", Journal of Real-Time Image Processing, Vol.8, No.4, pp.403-410, 2013.

K. Wang, J. Chen, W. Cao, Y. Wang, L. Wang and J. Tong, "A reconfigurable multi-transform VLSI architecture supporting video codec design", IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.58, No.7, pp.432-436, 2011.

W.-H. Chen, C. Smith and S. Fralick, "A fast computational algorithm for the discrete cosine transform", IEEE Transactions on Communications, Vol.25, No.9, pp.1004-1009, 1977.

Relative Articles

Supplements(0)

Cited By

Proportional views