JIANG Mei, LI Yongquan, YANG Zhi. A 3.9ppm/℃ 8.8nW and High PSRR Subthreshold CMOS Multiple Voltage Reference[J]. Chinese Journal of Electronics, 2017, 26(1): 101-105. doi: 10.1049/cje.2016.11.005
Citation: JIANG Mei, LI Yongquan, YANG Zhi. A 3.9ppm/℃ 8.8nW and High PSRR Subthreshold CMOS Multiple Voltage Reference[J]. Chinese Journal of Electronics, 2017, 26(1): 101-105. doi: 10.1049/cje.2016.11.005

A 3.9ppm/℃ 8.8nW and High PSRR Subthreshold CMOS Multiple Voltage Reference

doi: 10.1049/cje.2016.11.005
Funds:  This work was supported by the New Strategic Industry of Shenzhen China (No.JCYJ20140418091413578).
  • Received Date: 2014-09-14
  • Rev Recd Date: 2015-05-28
  • Publish Date: 2017-01-10
  • A voltage reference with low Temperature coefficient (TC) and three outputs, which is compatible with high Power supply rejection ratio (PSRR) and low power consumption, is presented in this paper. The proposed reference circuit operating with all transistors biased in subthreshold region, provides three reference voltages of 340mV, 680mV, and 1020mV. Subthreshold MOSFET design allows the circuit to work with minimum current consumption of 7.4nA at the supply voltage 1.2V. The mean line sensitivity is 1.7%/V under a supply voltages ranging from 1.2 to 3V. The Power supply rejection ratio (PSRR) of 340mV output voltage simulated at 100Hz and 10MHz is over than 51.9dB and 120.4dB, respectively. Monte Carlo simulation shows a mean TC is 3.9ppm/℃ with a standard deviation of 1ppm/℃ over a set of 500 samples, in a temperature range from -30℃ to 100℃. The active area of the presented voltage reference is 0.003mm2.
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