WANG Xiumin, GE Tingting, LI Jun, SU Chen, HONG Fangfei. Efficient Multi-rate Encoder of QC-LDPC Codes Based on FPGA for WIMAX Standard[J]. Chinese Journal of Electronics, 2017, 26(2): 250-255. doi: 10.1049/cje.2017.01.006
Citation: WANG Xiumin, GE Tingting, LI Jun, SU Chen, HONG Fangfei. Efficient Multi-rate Encoder of QC-LDPC Codes Based on FPGA for WIMAX Standard[J]. Chinese Journal of Electronics, 2017, 26(2): 250-255. doi: 10.1049/cje.2017.01.006

Efficient Multi-rate Encoder of QC-LDPC Codes Based on FPGA for WIMAX Standard

doi: 10.1049/cje.2017.01.006
Funds:  This work is supported by the National Natural Science Foundation of China (No.61379027), and Jiangsu Postdoctoral Foundation (No.1302059B).
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  • Corresponding author: GE Tingting (corresponding author) was born in 1990. She is pursuing a Master's Degree in signal processing in China Jiliang University. Her research interests include channel coding and decoding. (Email:836656440@qq.com)
  • Received Date: 2015-09-16
  • Rev Recd Date: 2016-06-10
  • Publish Date: 2017-03-10
  • An efficient multi-rate encoder for IEEE 802.16e LDPC codes which outperforms current single rate encoders with acceptable hardware consumption and efficient memory consumption is proposed. This design utilizes the common dual-diagonal structure in parity matrices to avoid the inverse matrix operation which requires extensive computations. Parallel Matrix-vector multiplication (MVM) units, bidirectional operation and storage compression are applied to this multi-rate encoder to increase the encoding speed and significantly reduce the quantity of memory bits required. The proposed encoding architecture also contributes to the design of multi-rate encoders whose parity matrices are dual-diagonally structured and have an Approximately lower triangular (ALT) form, such as in IEEE 802.11n and IEEE 802.22. Simulation results verified that the proposed encoder can efficiently work for all code rates specified in WIMAX standard. With a maximum clock frequency of 117 MHz, the encoder achieves 3 to 10 times higher throughput than prior works. The proposed encoder is capable to switch among six rates by adjusting the input parameter and it achieves the throughput up to 1Gbps.
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