HUO Yuanhong and LIU Dake, “High-Throughput Area-Efficient Processor for Cryptography,” Chinese Journal of Electronics, vol. 26, no. 3, pp. 514-521, 2017, doi: 10.1049/cje.2017.03.004
Citation: HUO Yuanhong and LIU Dake, “High-Throughput Area-Efficient Processor for Cryptography,” Chinese Journal of Electronics, vol. 26, no. 3, pp. 514-521, 2017, doi: 10.1049/cje.2017.03.004

High-Throughput Area-Efficient Processor for Cryptography

doi: 10.1049/cje.2017.03.004
Funds:  This work is supported by the National High-Tech Research and Development Program (863 Program) of China (No.2014AA01A705).
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  • Corresponding author: LIU Dake (corresponding author) was born in 1957. He is currently a professor and the head of the Institute of Application Specific Instruction Set Processors (ASIP), Beijing Institute of Technology, Beijing, China, and also a professor of Linköping University. He is enrolled in the China Recruitment Program of Global Experts. (
  • Received Date: 2016-01-12
  • Rev Recd Date: 2016-10-19
  • Publish Date: 2017-05-10
  • Cryptography circuits for portable electronic devices provide user authentication and secure data communication. These circuits should, achieve high performance, occupy small chip area, and handle several cryptographic algorithms. This paper proposes a highperformance ASIP (Application specific instruction set processor) for five standard cryptographic algorithms including both block ciphers (AES, Camellia, and ARIA) and stream ciphers (ZUC and SNOW 3G). The processor reaches ASIC-like performance such as 11.6 Gb/s for AES encryption, 16.0 Gb/s for ZUC, and 32.0 Gb/s for SNOW 3G, etc under the clock frequency of 1.0 GHz with the area consumption of 0.56 mm2 (65 nm). Compared with stateof-the-art VLSI designs, our design achieves high performance, low silicon cost, low power consumption, and sufficient programmability. For its programmability, our design can offer algorithm modification when an algorithm supported is unfortunately cracked and invalid to use. The product lifetime of our design can thus be extended.
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  • J.G. Andrews, S. Buzzi, W. Choi, et al., "What will 5G be?", IEEE Journal on Selected Areas in Communications, Vol.32, No.6, pp.1065-1082, 2014.
    ETSI/SAGE Specification, "Specification of the 3GPP Confidentiality and Integrity Algorithms UEA2& UIA2. Document 2:SNOW 3G Specification", version 1.1, 2006.
    D. Selent, "Advanced encryption standard", Rivier Academic Journal, Vol.6, No.2, pp.1-14, 2010.
    ETSI/SAGE Specification, "Specification of the 3GPP Confidentiality and Integrity Algorithms 128-EEA3& 128-EIA3. Document 2:ZUC Specification", version 1.5, 2011.
    S.S. Gupta, A. Chattopadhyay and A. Khalid, "HiPAcc-LTE:An integrated high performance accelerator for 3GPP LTE stream ciphers", International Conference on Cryptology in India, Chennai, India, pp.196-215, 2011.
    G. Sayilar and D. Chiou, "Cryptoraptor:High throughput reconfigurable cryptographic processor", Proceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, pp.154-161, 2014.
    Y. Eslami, A. Sheikholeslami, P.G. Gulak, et al., "An areaefficient universal cryptography processor for smart cards", IEEE Transactions on Very Large Scale Integration Systems, Vol.14, No.1, pp.43-56, 2006.
    K. Aoki, T. Ichikawa, M. Kanda, et al., "Specification of Camellia-A 128-bit block cipher", 2000.
    D. Kwon, J. Kim, S. Park, et al., "New block cipher:ARIA", International Conference on Information Security and Cryptology, Seoul, Korea, pp.432-445, 2003.
    J.H. Kong, L.M. Ang and K.P. Seng, "A comprehensive survey of modern symmetric cryptographic solutions for resource constrained environments", Journal of Network and Computer Applications, Vol.49, pp.15-50, 2014.
    I. Verbauwhede, P. Schaumont and H. Kuo, "Design and performance testing of a 2.29 GB/s rijndael processor", IEEE Journal of Solid-State Circuits, Vol.38, No.3, pp.569-572, 2003.
    S.K. Mathew, F. Sheikh, M. Kounavis, et al., "53 Gb/s native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors", IEEE Journal of Solid-State Circuits, Vol.46, No.4, pp.767-776, 2011.
    C. Zeng, N. Wu, X. Zhang, et al., "The optimization circuit design of AES S-Box based on a multiple-term common subexpression elimination algorithm", Acta Electronica Sinica, Vol.42, No.6, pp.1238-1243, 2014. (in Chinese)
    S. Qu, G. Shou, Y. Hu, et al., "High throughput, pipelined implementation of AES on FPGA", International Symposium on Information Engineering and Electronic Commerce, Ternopil, Ukraine, pp.542-545, 2009.
    M. Matsui and J. Nakajima, "On the power of bitslice implementation on Intel Core2 processor", International Workshop on Cryptographic Hardware and Embedded Systems, Vienna, Austria, pp.121-134, 2007.
    B. Liu and B.M. Baas, "Parallel AES encryption engines for many-core processor arrays", IEEE Transactions on Computers, Vol.62, No.3, pp.536-547, 2013.
    S.A. Manavski, "CUDA compatible GPU as an efficient hardware accelerator for AES cryptography", IEEE International Conference on Signal Processing and Communications, Dubai, United arab emirates, pp.65-68, 2007.
    T. Wollinger, M. Wang, J. Cuajardo, et al., "How well are highend DSPs suited for the AES algorithm?", The Third Advanced Encryption Standard Candidate Conference, pp.94-105, 2000.
    B. Koo, G. Ryu, T. Chang, et al., "Design and implementation of unified hardware for 128-bit block ciphers ARIA and AES", ETRI journal, Vol.29, No.6, pp.820-822, 2007.
    B. Wang and L. Liu, "A flexible and energy-efficient reconfigurable architecture for symmetric cipher processing", 2015 IEEE International Symposium on Circuits and Systems, Lisbon, Portugal, pp.1182-1185, 2015.
    S. Morioka and A. Satoh, "A 10-Gbps full-AES crypto design with a twisted BDD S-box architecture", IEEE Transactions on Very Large Scale Integration Systems, Vol.12, No.7, pp.686-691, 2004.
    L. Ali, I. Aris, F.S. Hossain, et al., "Design of an ultra high speed AES processor for next generation IT security", Computers & Electrical Engineering, Vol.37, No.6, pp.1160-1170, 2011.
    M. McLoone and J.V. McCanny, "High performance singleChip FPGA Rijndael algorithm implementations", International Workshop on Cryptographic Hardware and Embedded Systems, Paris, France, pp.65-76, 2001.
    X. Zhang and K.K. Parhi, "High-speed VLSI architectures for the AES algorithm", IEEE Transactions on Very Large Scale Integration Systems, Vol.12, No.9, pp.957-967, 2004.
    A. Hodjat and I. Verbauwhede, "Speed-area trade-off for 10 to 100 Gbits/s throughput AES processor", Conference Record of the Thirty-Seventh Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Vol.2, pp.2147-2150, 2003.
    A. Mericas, N. Peleg, L. Pesantez, et al., "IBM POWER8 performance features and evaluation", IBM Journal of Research and Development, Vol.59, No.1, 2015.
    N. Nishikawa, K. Iwai and T. Kurokawa, "High-performance symmetric block ciphers on multicore CPU and GPUs", International Journal of Networking and Computing, Vol.2, No.2, pp.251-268, 2012.
    J. Huang, F. Miao, J. Lv, et al., "Mobile phone based portable key management", Chinese Journal of Electronics, Vol.22, No.1, pp.124-130, 2013.
    Y. Huo, X. Li, W. Wang, et al., "High performance tablebased architecture for parallel CRC calculation", The 21st IEEE International Workshop on Local and Metropolitan Area Networks, Beijing, China, pp.1-6, 2015.
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