High-Throughput Area-Efficient Processor for Cryptography

HUO Yuanhong; LIU Dake

doi:10.1049/cje.2017.03.004

Volume 26 Issue 3

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Article Navigation > Chinese Journal of Electronics > 2017 > 26(3): 514-521

HUO Yuanhong and LIU Dake, “High-Throughput Area-Efficient Processor for Cryptography,” Chinese Journal of Electronics, vol. 26, no. 3, pp. 514-521, 2017, doi: 10.1049/cje.2017.03.004

Citation:

HUO Yuanhong and LIU Dake, “High-Throughput Area-Efficient Processor for Cryptography,” Chinese Journal of Electronics, vol. 26, no. 3, pp. 514-521, 2017, doi: 10.1049/cje.2017.03.004

HUO Yuanhong and LIU Dake, “High-Throughput Area-Efficient Processor for Cryptography,” Chinese Journal of Electronics, vol. 26, no. 3, pp. 514-521, 2017, doi: 10.1049/cje.2017.03.004

Citation:

HUO Yuanhong and LIU Dake, “High-Throughput Area-Efficient Processor for Cryptography,” Chinese Journal of Electronics, vol. 26, no. 3, pp. 514-521, 2017, doi: 10.1049/cje.2017.03.004

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High-Throughput Area-Efficient Processor for Cryptography

doi: 10.1049/cje.2017.03.004

HUO Yuanhong¹,
LIU Dake^{1,2
,}

1.
School of Computer Science and Technology, Beijing Institute of Technology, Beijing 100081, China;
2.
School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China

Funds: This work is supported by the National High-Tech Research and Development Program (863 Program) of China (No.2014AA01A705).

More Information

Corresponding author: LIU Dake (corresponding author) was born in 1957. He is currently a professor and the head of the Institute of Application Specific Instruction Set Processors (ASIP), Beijing Institute of Technology, Beijing, China, and also a professor of Linköping University. He is enrolled in the China Recruitment Program of Global Experts. (Email:dake@bit.edu.cn)
Received Date: 2016-01-12
Rev Recd Date: 2016-10-19
Publish Date: 2017-05-10

Abstract

Abstract

Cryptography circuits for portable electronic devices provide user authentication and secure data communication. These circuits should, achieve high performance, occupy small chip area, and handle several cryptographic algorithms. This paper proposes a highperformance ASIP (Application specific instruction set processor) for five standard cryptographic algorithms including both block ciphers (AES, Camellia, and ARIA) and stream ciphers (ZUC and SNOW 3G). The processor reaches ASIC-like performance such as 11.6 Gb/s for AES encryption, 16.0 Gb/s for ZUC, and 32.0 Gb/s for SNOW 3G, etc under the clock frequency of 1.0 GHz with the area consumption of 0.56 mm² (65 nm). Compared with stateof-the-art VLSI designs, our design achieves high performance, low silicon cost, low power consumption, and sufficient programmability. For its programmability, our design can offer algorithm modification when an algorithm supported is unfortunately cracked and invalid to use. The product lifetime of our design can thus be extended.
- ASIP (Application specific instruction set processor),
- Cryptographic processor,
- VLSI (Very largescale integration),
- Cryptography

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References(29)

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