Feedback Learning Based Dead Write Termination for Energy Efficient STT-RAM Caches

SHEN Fanfan; HE Yanxiang; ZHANG Jun; JIANG Nan; LI Qing'an; LI Jianhua

doi:10.1049/cje.2017.03.014

Volume 26 Issue 3

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SHEN Fanfan, HE Yanxiang, ZHANG Jun, et al., “Feedback Learning Based Dead Write Termination for Energy Efficient STT-RAM Caches,” Chinese Journal of Electronics, vol. 26, no. 3, pp. 460-467, 2017, doi: 10.1049/cje.2017.03.014

Citation:

SHEN Fanfan, HE Yanxiang, ZHANG Jun, et al., “Feedback Learning Based Dead Write Termination for Energy Efficient STT-RAM Caches,” Chinese Journal of Electronics, vol. 26, no. 3, pp. 460-467, 2017, doi: 10.1049/cje.2017.03.014

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Feedback Learning Based Dead Write Termination for Energy Efficient STT-RAM Caches

doi: 10.1049/cje.2017.03.014

1.
Computer School, Wuhan University, Wuhan 430072, China;
2.
State Key Laboratory of Software Engineering, Wuhan University, Wuhan 430072, China;
3.
School of Computer and Information, Hefei University of Technology, Hefei 230000, China

Funds: This work is supported by the National Natural Science Foundation of China (No.91118003, No.61170022, No.61373039, No.61402145, No.61502346), the Natural Science Foundation of Hubei Province (No.2015CFB338), the Natural Science Foundation of Anhui Province (No.1508085QF138), and the Science and Technology Project of Jiangxi Province Education Department (No.GJJ150605).

More Information

Corresponding author: HE Yanxiang (corresponding author) was born in 1952. He is a professor and Ph.D. supervisor at Wuhan University. His research interests include compiler theory, trusted software and software engineering. (Email:yxhe@whu.edu.cn)
Received Date: 2015-11-17
Rev Recd Date: 2016-03-17
Publish Date: 2017-05-10

Abstract

Abstract

Spin-torque transfer RAM (STT-RAM) is a promising candidate to replace SRAM for larger Last level cache (LLC). However, it has long write latency and high write energy which diminish the benefit of adopting STT-RAM caches. A common observation for LLC is that a large number of cache blocks have never been referenced again before they are evicted. The write operations for these blocks, which we call dead writes, can be eliminated without incurring subsequent cache misses. To address this issue, a quantitative scheme called Feedback learning based dead write termination (FLDWT) is proposed to improve energy efficiency and performance of STT-RAM based LLC. FLDWT dynamically learns the block access behavior by using data reuse distance and data access frequency, and then classifies the blocks into dead blocks and live blocks. FLDWT terminates dead write block requests and improves the estimation accuracy via feedback information. Compared with STT-RAM baseline in the lastlevel caches, experimental results show that our scheme achieves energy reduction by 44.6% and performance improvement by 12% on average with negligible overhead.
- Dead blocks,
- Energy efficiency,
- Spintransfer torque RAM (STT-RAM),
- Last level cache (LLC)

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References(19)

References

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