CAO Zhengcai, HUANG Zhexiao, LIU Min. A Performance Driven Lot Merging Method with Closed Loop Optimization for Semiconductor Wafer Fabrication[J]. Chinese Journal of Electronics, 2017, 26(5): 912-918. doi: 10.1049/cje.2017.08.019
Citation: CAO Zhengcai, HUANG Zhexiao, LIU Min. A Performance Driven Lot Merging Method with Closed Loop Optimization for Semiconductor Wafer Fabrication[J]. Chinese Journal of Electronics, 2017, 26(5): 912-918. doi: 10.1049/cje.2017.08.019

A Performance Driven Lot Merging Method with Closed Loop Optimization for Semiconductor Wafer Fabrication

doi: 10.1049/cje.2017.08.019
Funds:  This work is supported by the National Natural Science Foundation of China (No.51375038), the Doctoral Fund of Ministry of Education of China (No.20130010110009), and the Beijing Municipal Natural Science Foundation (No.4162046).
  • Received Date: 2015-06-24
  • Rev Recd Date: 2015-12-25
  • Publish Date: 2017-09-10
  • This paper deals with lot merging problem in semiconductor wafer fabrication system. There is the possibility to merge two or more partial lots into single lot if their subsequent process routes are the same, an improved lot merging method is presented by grouping lots belonging to different orders. Based on job information extracted from the buffers, several bin packing and knapsack solving algorithms are used to determine which lots should be merged. An iterative improvement procedure is introduced for optimizing merging strategy through a heuristic algorithm with resetting the ready time of critical lots. The closed loop structure with global revision factor is built for minimizing the impact of uncertain events while balancing the different orders processing progress. Applied to a simulation semiconductor manufacturing fab, the proposed algorithm can reduce cycle time and tardiness compared with other methods currently.
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