DING Yanyu, HU Jianguo, WANG Deming, TAN Hongzhou. A High-Performance RSA Coprocessor Based on Half-Carry-Save and Dual-Core MAC Architecture[J]. Chinese Journal of Electronics, 2018, 27(1): 70-75. doi: 10.1049/cje.2017.11.013
Citation: DING Yanyu, HU Jianguo, WANG Deming, TAN Hongzhou. A High-Performance RSA Coprocessor Based on Half-Carry-Save and Dual-Core MAC Architecture[J]. Chinese Journal of Electronics, 2018, 27(1): 70-75. doi: 10.1049/cje.2017.11.013

A High-Performance RSA Coprocessor Based on Half-Carry-Save and Dual-Core MAC Architecture

doi: 10.1049/cje.2017.11.013
Funds:  This work was supported by National Natural Science Foundation of China (No.61402546).
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  • Corresponding author: HU Jianguo (corresponding author) received Ph.D. degree in communication and information systems from Sun Yat-sen University, in 2010. He is a senior engineer of Sun Yat-sen University. His current research interests include integrated circuit, the Internet of things technology and application, smart city technology and application, embedded system. (Email:hujguo@mail.sysu.edu.cn)
  • Received Date: 2015-11-18
  • Rev Recd Date: 2015-11-18
  • Publish Date: 2018-01-10
  • This research focuses on the methods to improve the throughput and lower the power for low cost RSA coprocessors. We proposed the following optimized methods:1. A fast half-carry-save Montgomery modular multiplication algorithm suitable for hardware implementation; 2. A high-speed dual-core multiplier accumulator architecture to optimize the critical path; 3. Several lowpower optimization schemes for the RSA coprocessor. The design has been implemented with TSMC 90nm technology, and the experimental results show that the critical path is 2.71ns, the power consumption is just 9.76mW and the throughput can reach 381.57kbps. Compared with relative works, our design is featured by the minimal power and the best overall performance, thus it is most suitable for applications in low-power systems.
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