YUAN Hengzhou, GUO Yang, LIU Yao, LIANG Bin, GUO Qiancheng. A Self-Biased Low-Jitter Process-Insensitive Phase-Locked Loop for 1.25 Gb/s-6.25Gb/s SerDes[J]. Chinese Journal of Electronics, 2018, 27(5): 1009-1014. doi: 10.1049/cje.2018.02.003
Citation: YUAN Hengzhou, GUO Yang, LIU Yao, LIANG Bin, GUO Qiancheng. A Self-Biased Low-Jitter Process-Insensitive Phase-Locked Loop for 1.25 Gb/s-6.25Gb/s SerDes[J]. Chinese Journal of Electronics, 2018, 27(5): 1009-1014. doi: 10.1049/cje.2018.02.003

A Self-Biased Low-Jitter Process-Insensitive Phase-Locked Loop for 1.25 Gb/s-6.25Gb/s SerDes

doi: 10.1049/cje.2018.02.003
Funds:  This work is supported by the National Natural Science Foundation of China (No.61772540).
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  • Corresponding author: GUO Yang (corresponding author) was born in Zhejiang. He received the Ph.D. degree in Microelectronics and Solid State Electronics from National University of Defence Technology, China. He is a professor of National University of Defence Technology. His research interests include high speed analog circuits and electronic design automation algorithm. (Email:guoyang@nudt.edu.cn)
  • Received Date: 2016-02-26
  • Rev Recd Date: 2016-08-17
  • Publish Date: 2018-09-10
  • The paper presents a fully integrated multiphase output low-jitter CMOS phase-locked loop for 1.25Gb/s to 6.25Gb/s wireline SerDes transmitter clocking. The self-biased bandwidth technology with simplified structure is applied to reduce the sensitivity to process variations. A differential Charge pump (CP) which is suitable for low power supply and process migration is proposed. An accelerator is built to avoid the disadvantage of great damping factor. Self-adaptive frequency dividers are used to improve power efficiency. The simulation results under 65nm and 55nm process almost maintain almost the same jitter performance and show the high process insensitivity and good jitter performance.
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  • ALS. Loke, et al., “A versatile 90-nm CMOS charge-pump PLL for SerDes transmitter clocking”, IEEE J. Solid-State Circuits, Vol.41, No.8, pp.1894-1907, 2006.
    B.Y. Chi, et al., “1GHz monolithic fractional 2N frequency synthesizer with a 32b Third-Order Delta-Sigma modulator”, Acta Electronica Sinica, Vol.33, No.8, pp.1492-1496, 2005. (in Chinese)
    J. Tian, et al., “Study of mean time to lose lock and lock detector threshold in GPS carrier tracking loops”, Chinese Journal of Electronics, Vol.1, No.1, pp.46-50, 2013.
    J. Maneatis, et al., “Low-jitter process-independent DLL and PLL based on self-biased techniques”, IEEE J. Solid-State Circuits, Vol.31, No.11, pp.1723-1732, 1996.
    H. YUAN, et al., “A 40nm/65nm process adaptive low jitter phase-locked loop”, Proc. 14th International Symposium on Integrated Circuits (ISIC), Singapore, pp.500-503, 2014.
    T.F. Keefe and W.T. Tsai, “Multilevel concurrency control for multilevel secure database systems”, Proc. of IEEE Symposium on Security and Privacy, Oakland, California, USA, pp.25-28, 1990.
    M. Yuan, et al., “A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CMOS”, Proc. International Solid-state Circuits Conference, San Francisco, California, USA, pp.1-3, 2015.
    N. Autogust, et al., “A TDC-less ADPLL with 200-to-3200MHz range and 3mW power dissipation for mobile SoC clocking in 22n CMOS”, Proc. International Solid-state Circuits Conference, San Francisco, California, USA, pp.246-247, 2013.
    B.Y. Chi, et al., “New design method of LC VCO improving PVT tolerance of phase noise”, Chinese Journal of Electronics, Vol.24, No.3, pp.550-551, 2015.
    H. YUAN, et al., “An adaptive multi-modulus frequency divider”, Proc. The 10th IEEE International Conference on ASIC, Shenzhen, Guangdong, CHINA, pp.550-554, 2013.
    Y. Huang, et al., “A 2.4GHz ADPLL with digital-regulated supply noise insensitive and temperature self compensated ring DCO”, Proc. International Solid-state Circuits Conference, San Francisco, California, USA, pp.270-271, 2014.
    J. Liu, et al., “A 0.012mm23.1mW bang-bang digital fractionalN PLL with a power-supply-noise cancellation technique and a walking one phase selection fractional frequency divider”, Proc. International Solid-state Circuits Conference, San Francisco, California, USA, pp.268-269, 2014.
    D. Fischette, et al., “A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol IO”, Proc. International Solidstate Circuits Conference, San Francisco, California, USA, pp.246-247, 2010.
    M. Brownlee, et al., “A 0.5 to 2.5GHz PLL with fully differential supply regulated tuning”, IEEE J. Solid-State Circuits, Vol.41, No.12, pp.2720-2728, 2007.
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