LIU Haitao, WU Junjie, ZHANG Lizheng, DENG Qing, SUN Jie. A 14b 250MSps Pipelined ADC with Digital Self-calibration in 0.18μm CMOS Process[J]. Chinese Journal of Electronics, 2018, 27(3): 535-539. doi: 10.1049/cje.2018.03.009
Citation: LIU Haitao, WU Junjie, ZHANG Lizheng, DENG Qing, SUN Jie. A 14b 250MSps Pipelined ADC with Digital Self-calibration in 0.18μm CMOS Process[J]. Chinese Journal of Electronics, 2018, 27(3): 535-539. doi: 10.1049/cje.2018.03.009

A 14b 250MSps Pipelined ADC with Digital Self-calibration in 0.18μm CMOS Process

doi: 10.1049/cje.2018.03.009
  • Received Date: 2015-12-21
  • Rev Recd Date: 2016-10-31
  • Publish Date: 2018-05-10
  • A 14-bit pipelined Analog-to-digital converter (ADC) with a single-side digital self-calibration in a 0.18μm CMOS process is presented. The single-side foreground digital self-calibration is introduced to reduce the nonlinearity caused by capacitor mismatches. The ADC has a front-end Sample-and-hold (SH) circuit, followed by 13 1.5bit/stage sub-ADC and 2bit flash ADC at last. Test results show that, with a 140MHz input and 200MHz sampling rate, the SIAND is improved from 59dB to 66dB and SFDR is improved from 62dBc to 82dBc with the digital calibration. The measured SFDR reaches 77dBc even at 250MSps after calibration. The total power dissipation is 398mW at 250MSps including the parallel Low voltage differential signal (LVDS) output drivers.
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  • S.Y. Chuang and T.L. Sculley, "A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter", IEEE Journal of Solid-State Circuits, Vol.37, No.6, pp.674-683, 2002.
    K. Wang, C.J. Fan, W.J. Pan, et al., "Nonlinearity calibration for pipelined ADCs by splitting capacitors with self-tracking comparator thresholds", Chinese Journal of Electronics, Vol.24, No.3, pp.474-479, 2015.
    S.J. Liu, L. Zhou, W.S. Jiang, et al., "Channel mismatches correction in time-interleaved ADCs based on hybrid filter bank reconstruction", Chinese Journal of Electronics, Vol.23, No.1, pp.75-80, 2014.
    B. Lee, B. Min, G. Manganaro, et al., "A 14-b 100-MS/s pipelined ADC with a merged SHA and first MDAC", IEEE Journal of Solid-State Circuits, Vol.43, No.12, pp.2613-2619, 2008.
    S. Devarajan, L. Singer, D. Kelly, et al., "A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS pipeline ADC", IEEE Journal of Solid-State Circuits, Vol.44, No.12, pp.3305-3313, 2009.
    S.T. Ryu, B.S. Song and K. Bacrania, "A 10-bit 50-MS/s pipelined ADC with opamp current reuse", IEEE Journal of Solid-State Circuits, Vol.42, No.3, pp.475-485, 2007.
    J. Hu, N. Dolev and B. Mermann, "A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic source follower residue amplification", IEEE Journal of Solid-State Circuits, Vol.44, No.4, pp.1057-1066, 2009.
    J. Li, R. Leboeuf, M. Courcy, et al., "A 1.8V 10b 210MS/s CMOS pipelined ADC featuring 86dB SFDR without calibration", IEEE Custom Integrated Circuits Conference, pp.317-320, 2007
    H. Choi, P.S. Yoo, G.C. Ahn, et al., "A 14b 150MS/s 140mW 2.0mm20.13um CMOS A/D converter for software-defined radio systems", International Journal of Circuit Theory and Applications, pp.135-147, 2010.
    B. Yu, C. Chen, Y. Zhu, et al., "A 14-bit 200-MS/s timeinterleaved ADC with sample-time error detection and cancelation", IEEE ASSCC, pp.349-352, 2011.
    L. Luo, K. Lin, L. Cheng, et al., "A digitally calibrated 14-bit linear 100-MS/s pipelined ADC with wideband sampling frontend", IEEE ESSCIRC, pp.472-475, 2009.
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