DAI Lan, GUO Hong, LIN Qipeng, XIA Yongxin, ZHANG Xiaobo, ZHANG Feng, FAN Dongyu. An In-Memory-Computing Design of Multiplier Based on Multilevel-Cell of Resistance Switching Random Access Memory[J]. Chinese Journal of Electronics, 2018, 27(6): 1151-1157. doi: 10.1049/cje.2018.08.006
Citation: DAI Lan, GUO Hong, LIN Qipeng, XIA Yongxin, ZHANG Xiaobo, ZHANG Feng, FAN Dongyu. An In-Memory-Computing Design of Multiplier Based on Multilevel-Cell of Resistance Switching Random Access Memory[J]. Chinese Journal of Electronics, 2018, 27(6): 1151-1157. doi: 10.1049/cje.2018.08.006

An In-Memory-Computing Design of Multiplier Based on Multilevel-Cell of Resistance Switching Random Access Memory

doi: 10.1049/cje.2018.08.006
Funds:  This work is supported by the National Key R&D Program of China (No.2018YFB0407502), the National Natural Science Foundation of China (No.61674087, No.61674092, No.61474134), and the Research Fund from Beijing Innovation Center for Future Chip (No.KYJJ2016007).
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  • Corresponding author: FAN Dongyu (corresponding author) was born in 1991. He received the B.S. degree from Shandong University, Shandong. He received the M.S. degree from North China University of Technology, Beijing. His research interest is memory circuits design. He studied in Institute of Microelectronics of Chinese Academy of Sciences from 2016 to 2018. (Email:839658905@qq.com)
  • Received Date: 2018-03-23
  • Rev Recd Date: 2018-05-14
  • Publish Date: 2018-11-10
  • Due to the Von Neumann bottleneck, in-memory-computing, as a new architecture, has drawn considerable attention and is becoming an candidate of next generation electronics system. It presents an inmemory-computing approach for multiplier design based on Multilevel-cell (MLC) of Resistive random access memories (RRAMs). The paper proposes a Look-up-table (LUT) operations to optimize the speed, area and power of the multiplier circuits. The proposed MLC function of RRAM revealed that RRAM could have a multilevel stable resistance by adjusting the operating voltage. The simulation results show that, taking a 16-bits multiplier as an example, the circuits of this paper has a calculation speed that is increased by 35.7 percent and an area that is decreased by 14 percent under the similar power consumption conditions when compared with other traditional 16-bits multiplier.
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