SHANG Xinchao, SHAN Weiwei, XIANG Yiming, WAN Liang, FAN Ao. Low Overhead and Fast Reaction Adaptive Clocking System for Voltage Droop Tolerance[J]. Chinese Journal of Electronics, 2019, 28(3): 503-507. doi: 10.1049/cje.2019.02.009
Citation: SHANG Xinchao, SHAN Weiwei, XIANG Yiming, WAN Liang, FAN Ao. Low Overhead and Fast Reaction Adaptive Clocking System for Voltage Droop Tolerance[J]. Chinese Journal of Electronics, 2019, 28(3): 503-507. doi: 10.1049/cje.2019.02.009

Low Overhead and Fast Reaction Adaptive Clocking System for Voltage Droop Tolerance

doi: 10.1049/cje.2019.02.009
Funds:  This work is supported by National Natural Science Foundation of China (No.61574033, No.61774038), and National 863 project (No.2015AA016601).
  • Received Date: 2017-03-30
  • Publish Date: 2019-05-10
  • Variation in on-chip power supply continues to be a major challenge to limit circuit performance. To mitigate the impact of high-frequency voltage droop, a novel all-digital adaptive clock system is proposed. The adaptive clock system is composed of a droop detector and an adaptive clock generator, which directly stretch the clock period when the circuit suffers from the supply voltage droop. The droop detector circuit detects the VDD droop and the digital adaptive clock generator circuit selects the stretched clock to prevent timing-margin failures. The response time for droop detection and clock stretch can be as fast as one cycle. The whole scheme is used on a test circuit under SMIC 40nm CMOS process with a layout area of 900um*1100um. Postlayout simulation results demonstrate power reductions are 7% at 1.1V and 15% at 0.7V for a 10% VDD droop, respectively.
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