Citation: | DING Dandan, WANG Silong, LIU Zoe, et al., “Real-Time H.265/HEVC Intra Encoding with a Configurable Architecture on FPGA Platform,” Chinese Journal of Electronics, vol. 28, no. 5, pp. 1008-1017, 2019, doi: 10.1049/cje.2019.06.020 |
MPEG-H Part 2/ISO/IEC Standard 23008-2:2013, High Efficiency Video Coding (HEVC).
|
G. Sullivan, J. Ohm, W. Han, et al., "Overview of the high efficiency video coding (HEVC) standard", IEEE Transactions on Circuits and Systems for Video Technology, Vol.22, No.12, pp.1649-1668, 2012.
|
F. Bossen, B. Bross, K. Suhring, et al., "HEVC complexity and implementation analysis", IEEE Transactions on Circuits and Systems for Video Technology, Vol.22, No.12, pp.1685-1696, 2013.
|
W. Xiao, B. Li, J. Xu, et al., "HEVC encoding optimization using multicore CPUs and GPUs", IEEE Transactions on Circuits and Systems for Video Technology, Vol.25, No.12, pp.1830-1843, 2015.
|
J. Ma, F. Luo, S. Wang, et al., "Parallel intra coding for HEVC on CPU plus GPU platform", Visual Communications and Image Processing (VCIP), Singapore, 2015.
|
S. Radicke, J. Hahn, Q. Wang, et al., "A parallel HEVC intra prediction algorithm for heterogeneous CPU+GPU platforms", IEEE Transactions on Broadcasting, Vol.62, No.1, pp.103-119, 2016.
|
S. Radicke, J. Hahn, Q. Wang, et al., "Bi-predictive motion estimation for HEVC on a Graphics processing unit (GPU)", IEEE Transactions on Consumer Electronics, Vol.60, No.4, pp.728-736, 2014.
|
Y. Wang, X. Guo, Y. Lu, et al., "GPU-based optimization for sample adaptive offset in HEVC", IEEE International Conference on Image Processing (ICIP), Phoenix, Arizona, USA, pp.829-833, 2016.
|
F. Luo, S. Wang, N. Zhang, et al., "GPU based sample adaptive offset parameter decision and perceptual optimization for HEVC", IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, pp.2687-2690, 2016.
|
J. Kufa and T. Kratochvil, "Software and hardware HEVC encoding", International Conference on Systems, Signals and Image Processing (IWSSIP), Pozna, Poland, 2017.
|
J. Zhu, Z. Liu, D. Wang, Q. Han, et al., "HDTV 1080p HEVC intra encoder with source texture based CU/PU mode predecision", Proc. of 19th Asia South Pacific Design Autom. Conf. (ASP-DAC), Tokyo, Japan, pp.367-372, 2014.
|
S. Tsai, C. Li, H. Chen, et al., "A 1062M pixels/s 8192×4320p high efficiency video coding(H.265) encoder Chip", Symposium on VLSI Circuits (VLSIC), Kyoto, Japan, pp.C188-C189, 2013.
|
K. Miyazawa, H. Sakate, S. Sekiguchi, et al., "Real-time hardware implementation of HEVC video encoder for 1080p HD video," Picture Coding Symposium (PCS), San Jose, California, USA, pp.225-228, 2013.
|
S. Atapattu, N. Liyanage, N. Menuka, et al., "Real time all intra HEVC HD encoder on FPGA", IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), London, England, pp.191-95, 2016.
|
G. Pastuszak and A. Abramowski, "Algorithm and architecture design of the H.265/HEVC intra encoder", IEEE Transactions on Circuits and Systems for Video Technology, Vol.26, No.1, pp.210-222, 2016.
|
P. Helle, S. Oudin, B. Bross, et al., "Block merging for quadtree-based partitioning in HEVC", IEEE Transactions on Circuits and Systems for Video Technology, Vol.22, No.12, pp.1720-1731, 2012.
|
B. Lee and M. Kim, "A CU-Level rate and distortion estimation scheme for RDO of hardware-friendly HEVC encoders using low-complexity integer DCTs", IEEE Transactions on Image Processing, Vol.25, No.8, pp.3787-3800, 2016.
|
T. Ye, D. Zhang, F. Dai, et al., "Fast mode decision algorithm for intra prediction in HEVC", ACM International Conference on Internet Multimedia Computing and Service, Huangshan, China, pp.300-304, 2013.
|