ROY Suvajit, PAL Radha-Raman. Single Fully Differential Second Generation Current Conveyor Based Four-Quadrant Analog Multiplier Design and Its Applications[J]. Chinese Journal of Electronics, 2020, 29(5): 959-965. doi: 10.1049/cje.2020.08.012
Citation: ROY Suvajit, PAL Radha-Raman. Single Fully Differential Second Generation Current Conveyor Based Four-Quadrant Analog Multiplier Design and Its Applications[J]. Chinese Journal of Electronics, 2020, 29(5): 959-965. doi: 10.1049/cje.2020.08.012

Single Fully Differential Second Generation Current Conveyor Based Four-Quadrant Analog Multiplier Design and Its Applications

doi: 10.1049/cje.2020.08.012
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  • Corresponding author: PAL Radha-Raman (corresponding author) was born in 1967 in West Bengal, India. He passed his B.Sc. (Hons) and M.Sc. degrees from Burdwan University, India in the years 1986 and 1988 respectively and topped the list in both the examinations. He got his Ph.D. degree from Indian Institute of Technology, Kharagpur, India in the year 1996. His Ph.D. topic was "Studies on voltage/current controlled oscillators using complementary bipolar inverter cells". He joined Bengal Engineering College (Deemed University)[now Indian Institute of Engineering, Science and Technology] as a Lecturer in Physics in the year 1995. Presently he is working as a Professor in Physics in the Vidyasagar University, Midnapore, India. His research interest is Low voltage/low power integrated circuit design, Universal filter, VCO and PLL design. (Email:rrpal@mail.vidyasagar.ac.in)
  • Received Date: 2018-09-17
  • Rev Recd Date: 2020-07-13
  • Publish Date: 2020-09-10
  • This manuscript presents a new fourquadrant analog multiplier using a recently reported current mode active building block, namely the Fully differential second generation current conveyor (FDCCII). The proposed circuit employs single FDCCII and two NMOSFETs only, thus has simple architecture. It is fully-integrable as no other external passive component has been used. Non-ideal behaviour of the reported configuration has been analysed considering current and voltage tracking errors of the FDCCII. Workability of the derived multiplier is verified with PSPICE (Cadence 16.6) simulations using model parameter of TSMC 0.35μm CMOS process and found to be in close agreement with theoretical anticipations. The static power consumption of the circuit is 0.107mW. The circuit works well with good linearity (nonlinearity error ≤ 0.96%) for the input voltage range of ±0.5V for a supply voltage of ±1V and the output is insensitive to temperature variation. Simulation results show that the -3dB bandwidth of the proposed multiplier is 20.67MHz and the output referred noise is less than 9nV/√Hz at 1kΩ load condition. MonteCarlo analysis has also been performed for the proposed configuration. The applicability of the reported multiplier as amplitude modulator, squarer, and frequency doubler are also demonstrated.
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