An Improved Global Shutter Pixel with Extended Output Range and Linearity of Compensation for CMOS Image Sensor

GUO Zhongjie; YU Ningmei; WU Longsheng

doi:10.1049/cje.2020.11.007

Volume 30 Issue 1

Dec. 2020

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Article Contents

Abstract

Ⅰ. Introduction

Ⅱ. Extension Approach of Output Range

Ⅲ. Compensated Linearity with Negative Feedback Self-establishment

Ⅳ. Experimental Results and Discussion

Ⅴ. Conclusions

References

Chinese Journal of Electronics > 2021 > 30(1): 102-108. > DOI: 10.1049/cje.2020.11.007

GUO Zhongjie, YU Ningmei, WU Longsheng. An Improved Global Shutter Pixel with Extended Output Range and Linearity of Compensation for CMOS Image Sensor[J]. Chinese Journal of Electronics, 2021, 30(1): 102-108. DOI: 10.1049/cje.2020.11.007

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An Improved Global Shutter Pixel with Extended Output Range and Linearity of Compensation for CMOS Image Sensor

1.
School of Automation and Information Engineering, Xi'an University of Technology, Xi'an 710048, China
2.
Xi'an Microelectronic Technology Institute, Xi'an 710054, China

Funds:

the National Natural Science Foundation of China 61771388

Scientific Research Project of Shaanxi Education Department 19JC029

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Author Bio:
YU Ningmei received the B.S. degree in electronic engineering from the Xi'an University of Technology, Xi'an, China, in 1986 and the M.S. and Ph.D. degrees in electronic engineering from Tohoku University, Sendai, Japan, in 1996 and 1999, respectively. She is currently a Professor with the Department of Electric Engineering, Xi'an University of Technology. Her current research interests include very large scale integration circuit design. (Email: yunm@xaut.edu.cn)

WU Longsheng received the M.S. degree in microelectronics and solidstate electronics and the Ph.D. degree in computer system structure from the Institute of Microelectronics Technology, Xi'an, China, in 1994 and 2001, respectively. His current research interests include solid state image sensors design, hardening device, or circuit design for space applications. (Email: wls771@163.com)
Corresponding author:
GUO Zhongjie (corresponding author) received the B.S. and M.S. degrees in Measurement and Control Technology and Instrumentation, and circuit and system from Xidian University, China, in 2004 and 2007, respectively, and Ph.D. degree in microelectronics engineering from Xi'an Microelectronic Technology Institute, China, in 2012. His current research interests include high performance mixed signal integration circuit design. (Email: zjguo@xaut.edu.cn)
Received Date: March 23, 2020
Accepted Date: July 29, 2020
Published Date: December 31, 2020

Graphical Abstract

Abstract

Abstract

An improved global shutter pixel structure with extended output range and linearity of compensation is proposed for CMOS image sensor. The potential switching of the sample and hold capacitor bottom plate outside the array is used to solve the problem of the serious swing limitation, which will attenuate the dynamic range of the image sensor. The non-linear problem caused by the substrate bias effect in the output process of the pixel source follower is solved by using the mirror FD point negative feedback self-establishment technology outside the array. The approach proposed in this paper has been verified in a global shutter CMOS image sensor with a scale of 1024×1024 pixels. The test results show that the output range is expanded from 0.95V to 2V, and the error introduced by the nonlinearity is sharply reduced from 280mV to 0.3mV. Most importantly, the output range expansion circuit does not increase the additional pixel area and the power consumption. The power consumption of linearity correction circuit is only 23.1μW, accounting for less than 0.01% of the whole chip power consumption.
- CMOS image sensor,
- Pixel,
- Global shutter,
- Output range,
- Linearity

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Ⅰ. Introduction

In recent years, Complementary metal oxide semiconductor (CMOS) image sensor has been widely used and made great progress due to the advanced process and the circuit design. CMOS image sensor is not only widely used in portable digital camera, mobile phone camera, hand-held camera, digital Single lens reflex (SLR) camera and other consumer electronic products, but also in smart car, satellite, security, robot vision and other fields. At the same time, there are also intelligent CMOS image sensors or CMOS image sensor integrated with intelligent processing function on chip^[1-5]. Due to the requirements of the shooting fast moving objects, the CMOS image sensor with global shutter must be used because the rolling shutter cannot meet the requirements in high-speed photography, automation and industrial applications^[6-9].

Pixel is the research foundation of a high-perfor-mance global shutter CMOS image sensor which can realize simultaneous reset and integration. At present, the research achievements in this area mainly include the following aspects. 1) Based on the 4T pixel structure, a reset transistor is added to realize the 5T pixel structure of a global shutter function^{[10, 11]}. However, in this structure, if FD node is used as the analog storage point of the global shutter, a large reset noise will be introduced and it is difficult to achieve low-noise performance index. At the same time, the structure cannot realize the true correlated double sampling technology, and eliminate the pixel level fixed pattern noise. 2) Adding a charge amplifier and a sample and hold circuit based on the 3T structure to form a 6T structure is another method. Because the parasitic capacitance of the FD node is relatively reduced, this structure can reduce the reset noise, improve the sensitivity, but increase the pixel area^[12-14]. 3) The third method is the 7T pixel structure based on the CCD technology. The charge excited by the light is transferred to the floating diffusion node FD through the transmission gate, the storage gate and the control gate. By adding the storage gate and the control gate, the pixel can have a storage node to store the charge of the image signal. The advantage of the 7T pixel is that the two signal samples can be executed in the same reset level integration cycle. Therefore, the KTC noise carried by the reset signal and the image signal are related, and the related noise can be eliminated by the correlation double sampling. However, the large power consumption, the complex structure and the incompatibility between the process and the mainstream silicon processing are the disadvantages of the 7T pixel structure. 4) On the basis of the 4T APS pixel, two storage nodes are added to form an 8T double capacitance global pixel circuit structure^[15]. Since the reset level and signal level are stored in the same cycle, the noise level of the output signal can be greatly reduced in the read-out phase through correlated double sampling. The 8T pixel structure can not only realize the true correlation double sampling of the traditional 4T pixel structure, but also can meet the requirements of the global shutter pixel technology. It is a more mature and popular global shutter pixel structure in the near future. However, there are still two key problems restricting its application. Firstly, there exists two-stage source follower in the readout processing of the 8T pixel structure, which will attenuate the voltage of the FD point, limit the swing of the pixel output, and reduce the dynamic range of the sensor. Secondly, in the process of the pixel output sampling, there is a certain non-linear error exists in the result of the difference between the reset signal and the image signal after two sampling due to the substrate bias effect of the source follower, which affects the linearity of the photoelectric response of the sensor.

Some progresses have been made in the research of the pixel output range expansion. New Complementary active pixel sensor (CAPS) architecture is designed and fabricated in a standard 0.25µm CMOS technology to recover the threshold voltage lost in the in-pixel amplifier and to improve the output swing of the CAPS close to rail-to-rail^[16]. However, the structure not only uses both PMOS and NMOS, but also requires two columns for each column of pixel output, which is unfavorable for the compact pixel array. In Ref.[17], the output range expansion using bootstrap technology is studied, and the pixel output range enhancement technology based on the bootstrap reset voltage and the power supply voltage is proposed. But this technology will introduce large power consumption and will be limited by the device breakdown voltage. Ref.[18] has improved the output range through subsequent programmable gain amplification. But this method will limit the actual swing, the full well capacity and the noise characteristics of the pixels, which are not conducive to the performance of the pixels. Although Ref.[19] gives a solution to extend output range for 4T or 5T APS, it is not suitable for 8T APS due to the in-pixel sampling. In the aspect of linearity correction of pixel output, the nonlinearity of pixel output is studied systematically in Ref.[20]. A novel pixel design based on a capacitive trans-impedance amplifier has proposed to achieve higher pixel-level linearity. But this technology will greatly increase the hardware overhead of the pixel, compress the filling factor of the pixel, and then affect the quantum efficiency of the sensor. In addition, the nonlinear ramp voltage is also used at the system level to counteract the nonlinear effect of the pixels, but this requires very high matching characteristics to ensure the nonlinearity of the pixels is consistent with that of the ramps. In particular, when the temperature changes as mentioned in Ref.[21], it is more necessary to consider the real-time matching in order to pursue higher linearity. Therefore, for the linearization correction mechanism of the pixel output, it is necessary to consider the real-time tracking characteristics of the correction mechanism and the characteristics of the introduction point close to the pixel sensitive point. We have carried out the basic research of the pixel linearization technology in the previous work^[22]. And this time we will improve the 8T pixel structure to increase the output linearity of this structure.

This paper focuses on the research and the analysis of the above two key issues, and proposes an effective solution outside the array on the chip. Without affecting the filling factor, the output range is doubled, and the linearity is increased by three orders of magnitude, which provides a technical solution for the wider application of the 8T global shutter CMOS image sensor. Section Ⅱ describes the pixel design with an extended output range. Section Ⅲ provides the linearization correction based on the negative feedback self-establishment. The prototype CMOS sensor chip experimental results which adopting the proposed approach are shown in Section Ⅳ. Finally, the conclusions of this brief are drawn in Section V.

Ⅱ. Extension Approach of Output Range

As shown in , the 8T pixel structure with global shutter function is mainly characterized by the addition of the sampling and holding capacitance on the basis of the traditional 4T pixel structure, in which $\mathrm{C}_{\mathrm{R}}$ is the sample and hold capacitance of the reset signal, $\mathrm{C}_{\mathrm{S}}$ is the sample and hold capacitance of the image signal. Before exposure, the FD point is reset, and the reset voltage is synchronously stored on capacitor $\mathrm{C}_{\mathrm{R}}$ through the transistors $\mathrm{M}_{\mathrm{S}\mathrm{F}1}$ , $\mathrm{M}_{\mathrm{S}1}$ and $\mathrm{M}_{\mathrm{S}2}$ . After exposure, the charge generated by the PPD point is transferred to FD point, and the integral voltage is synchronously stored on the capacitor $\mathrm{C}_{\mathrm{S}}$ through the transistors $\mathrm{M}_{\mathrm{S}\mathrm{F}1}$ and $\mathrm{M}_{\mathrm{S}1}$ . During line reading, the reset voltage on $\mathrm{C}_{\mathrm{R}}$ and the integral voltage on C_S are successively read through the transistors $\mathrm{M}_{\mathrm{S}\mathrm{F}2}$ and $\mathrm{M}_{\mathrm{S}2}$ . It can be seen that when the signal generated by the source photodiode is transmitted to the SP point, the image signal and the reset signal have been lost for an over driving voltage.

$\begin{equation} V_{S P}=V_{F D}-\left(V_{S F 1_- T H}+V_{S F 1_- O V}\right) \end{equation}$

(1)

$\begin{equation} V_{\text {out}}=V_{S P}-\left(V_{S F 2\_\text{TH}}+V_{S F 2\_\text {OV}}\right) \end{equation}$

(2)

Figure 1. Conventional 8T APS

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where $V_{SF\mathit{1}{\_{}}TH}$ and $V_{SF\mathit{1}{\_{}}OV}$ are, respectively, the threshold and over driving voltages of the source follower transistor $\mathrm{M}_{\mathrm{S}\mathrm{F}1}$ , $V_{SF\mathit{2}{\_{}}TH}$ and $V_{SF\mathit{2}{\_{}}OV}$ \textit{}are, respectively, the threshold and over driving voltages of the source follower transistor $\mathrm{M}_{\mathrm{S}\mathrm{F}2}$ . From the above two formulas, the relationship between the output node and the original signal of the photodiode can be obtained as follows.

$\begin{align*} V_{\text {out}}=&V_{F D}-\left(V_{S F 1_- T H}+V_{S F 1_- O V}\right)\\ &-\left(V_{S F 2_- T H}+V_{S F 2_- O V}\right) \end{align*}$

(3)

As shown in Fig. 2, the voltage attenuation in the signal transmission process is visually illustrated. The reset voltage of the left sampling stage has been reflected in FD, SP and OUT points from large to small. With the increasing of the exposure time, the OUT, SP and FD points will successively enter the cut-off state in the readout stage.

Figure 2. Limiting on output range

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In order to solve the problem of swing loss in the 8T pixel structure, an output range expansion method with high efficiency out of array is proposed in this paper. When the internal circuit of the pixel structure is unchanged, that is, the filling factor will not be reduced, the SP point voltage can be boosted by time-sharing switching the bottom plate potential of the C_R and C_S capacitors outside the array.

As shown in Fig. 3. The basic idea is to control the voltage of the common bottom plate in sample stage and readout stage to boost the absolute voltage on SP point. The programmable voltage outside the pixel array is V_C, which is the voltage rise of SP point. If Eq.(4) is workable,

$\begin{equation*} V_{C}=\left(V_{S F 1_- T H}+V_{S F 1_- o V}\right)+\left(V_{S F 2_- T H}+V_{S F 2_- O V}\right) \end{equation*}$

(4)

Figure 3. Proposed 8T APS topology

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Then combining Eqs.(3) and (4), we can get

$\begin{equation*} V_{O U T}=V_{F D} \end{equation*}$

(5)

Then the output swing can track the FD point swing, which will maximize the output range of the 8T pixels with true correlated double sampling. $V_{SF\mathit{1}{\_{}}TH}$ and $V_{SF\mathit{1}{\_{}}OV}$ added to $\mathrm{V}_{\mathrm{C}}$ are mainly to restore the FD point voltage at the pixel output node. In order to ensure the optimal $\mathrm{V}_{\mathrm{C}}$ value can be accurately controlled, the method adopted in this paper is to configure DAC analog output through SPI, so as to achieve the expansion degree of real-time monitoring pixel output. By using the correlated double sampling technology, the voltage of the bottom plate will not affect the performance of pixel. Since the capacitor is realized by MIM capacitor, it has little effect on PLS and leakage current.

shows the specific timing relationship of the circuit. We can divide the whole process into two phases, the sampling phase and the output phase. In the sampling phase, the bottom plate shared by $\mathrm{C}_{\mathrm{R}}$ and $\mathrm{C}_{\mathrm{S}}$ capacitors is connected to the ground through switch $\mathrm{S}_{3}$ . During this period, the reset signal is sampled by the capacitor $\mathrm{C}_{\mathrm{R}}$ at the falling edge of the switch $\mathrm{S}_{2}$ , and the image signal is sampled by the capacitor $\mathrm{C}_{\mathrm{S}}$ at the falling edge of the switch $\mathrm{S}_{1}$ . In the readout phase, the bottom plate shared by $\mathrm{C}_{\mathrm{R}}$ and $\mathrm{C}_{\mathrm{S}}$ capacitors is connected to $\mathrm{V}_{\mathrm{C}}$ through switch $\mathrm{S}_{4}$ . Due to the bottom plate sampling technology, the sampling signal voltage increases $\mathrm{V}_{\mathrm{C}}$ after the bottom plate potential switching, and does not affect the results of the correlated double sampling. At this time, firstly, when $\mathrm{S}_{2}$ is off, the reset signal on capacitor $\mathrm{C}_{\mathrm{R}}$ is output through $\mathrm{M}_{\mathrm{S}\mathrm{F}2\mathrm{A}}$ of the second source follower, and then when $\mathrm{S}_{2}$ is closed, the image signal held on capacitor $\mathrm{C}_{\mathrm{S}}$ is output through $\mathrm{M}_{\mathrm{S}\mathrm{F}2\mathrm{A}}$ of the second source follower. It can be seen that the method proposed in this paper effectively solves the problem of swing limitation of the 8T pixel.

Figure 4. Timing diagram of proposed 8T APS

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Ⅲ. Compensated Linearity with Negative Feedback Self-establishment

Due to the superior performance of the correlated double sampling technology, the voltage signal will be read twice during the reading process after the pixel photoelectric conversion. The first reading is the reset voltage signal $\mathrm{V}_{\mathrm{R}\mathrm{S}\mathrm{T}}$ , and the second reading is the image signal $\mathrm{V}_{\mathrm{S}\mathrm{I}\mathrm{G}}$ after integration. There is no difference of the voltage signal during the first reading process with different light intensity. The main difference is in the image signal $\mathrm{V}_{\mathrm{S}\mathrm{I}\mathrm{G}}$ during the second reading process. $\mathrm{V}_{\mathrm{S}\mathrm{I}\mathrm{G}}$ varies with the different light intensity or the exposure time of the same pixel. Because of the second-order effect of the substrate bias of the source follower $\mathrm{M}_{\mathrm{S}\mathrm{F}2\mathrm{A}}$ , the variation of the pixel output $\mathrm{V}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ is not linear with the variation of $\mathrm{V}_{\mathrm{S}\mathrm{I}\mathrm{G}}$ . When $\mathrm{V}_{\mathrm{S}\mathrm{I}\mathrm{G}}$ changes, the change of $\mathrm{V}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ causes the change of the threshold value of the source follower $\mathrm{M}_{\mathrm{S}\mathrm{F}2\mathrm{A}}$ , and then affects the linearity of the photoelectric signal output, as shown in the following equation.

$\begin{equation*} V_{T H}=V_{T H 0}+\gamma\left(\sqrt{\left|2 \Phi_{F}+V_{S B}\right|}-\sqrt{\left|2 \Phi_{F}\right|}\right) \end{equation*}$

(6)

where $\mathrm{V}_{\mathrm{S}\mathrm{B}}$ is the voltage difference between the source and the substrate of the MOS device, $\mathrm{V}_{\mathrm{T}\mathrm{H}0}$ is the threshold voltage when $\mathrm{V}_{\mathrm{SB}}=0, \Phi_{\mathrm{F}}$ is the equilibrium barrier of the semiconductor electrostatic. In view of this nonlinear problem, the research scheme of this paper mainly adopts the column level dynamic correction technology, through the negative feedback stabilization technology to restore the image signal before the sampling of the column level processing circuit.

shows the linearization circuit and its connection relationship with the pixel proposed in this project, in which $\mathrm{M}_{\mathrm{S}\mathrm{F}2}$ , $\mathrm{M}_{\mathrm{S}\mathrm{E}\mathrm{L}}$ and $\mathrm{M}_{\mathrm{T}\mathrm{C}}$ are the source follower input transistor, the row selection switch and the tail current source respectively, $\mathrm{M}_{\mathrm{S}\mathrm{F}2\mathrm{A}}$ , $\mathrm{M}_{\mathrm{S}\mathrm{E}\mathrm{L}\mathrm{A}}$ and $\mathrm{M}_{\mathrm{T}\mathrm{C}\mathrm{A}}$ are the same size devices as the first three, respectively, to form a pseudo pixel source follower. $\mathrm{M}_{\mathrm{S}\mathrm{E}\mathrm{L}\mathrm{A}}$ gate is connected to a high level, to ensure the matching with $\mathrm{M}_{\mathrm{S}\mathrm{E}\mathrm{L}}$ . In the linearization circuit, the positive and the negative input terminals of the operational amplifier are respectively connected with the output terminals of the useful pixel and the pseudo pixel source follower. The output terminal of the operational amplifier is the output of the linearization circuit, which is connected with the post-processing circuit. Due to the negative feedback effect of the operational amplifier, the voltage of the positive input is equal to the negative input, so the threshold voltage drift caused by the bias effect is the same, and the over driving voltage is the same, the output voltage completely follows the SP point voltage change, that is, the voltage signal of the linearization circuit completely reflects the light intensity information.

Figure 5. 8T global shutter pixel with linearity enhancement

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The mathematical derivation process is as follows in detail. Supposing that $\mathrm{V}_{\mathrm{R}\mathrm{S}\mathrm{T}{\_{}}1}$ , $\mathrm{V}_{\mathrm{S}\mathrm{I}\mathrm{G}{\_{}}1}$ is the reset voltage and the integral voltage of the FD point, $\mathrm{V}_{\mathrm{R}\mathrm{S}\mathrm{T}{\_{}}2}$ , $\mathrm{V}_{\mathrm{S}\mathrm{I}\mathrm{G}{\_{}}2}$ is the reset voltage and image voltage when sampling on the pixel SP point, $\Delta \mathrm{V}_{\mathrm{TH}}\_{\mathrm{RST}}, \Delta \mathrm{V}_{\mathrm{TH}\_\mathrm{SIG}}$ is the change or the threshold voltage of the source follower when the pixel outputs the reset voltage and image voltage respectively, $\mathrm{V}_{\mathrm{R}\mathrm{S}\mathrm{T}{\_{}}\mathrm{O}\mathrm{U}\mathrm{T}}$ , $\mathrm{V}_{\mathrm{S}\mathrm{I}\mathrm{G}{\_{}}\mathrm{O}\mathrm{U}\mathrm{T}}$ is the final output voltage. Because the $\mathrm{M}_{\mathrm{T}\mathrm{C}}$ of the pixel tailpipe and the $\mathrm{M}_{\mathrm{T}\mathrm{C}\mathrm{A}}$ of the output tailpipe are 1:1 matched image relationship, the current flowing through the source follower $\mathrm{M}_{\mathrm{S}\mathrm{F}2}$ and the output tube $\mathrm{M}_{\mathrm{S}\mathrm{F}2\mathrm{A}}$ is consistent. Therefore, the current voltage relationship in the two output processes of the source follower $\mathrm{M}_{\mathrm{S}\mathrm{F}2}$ is

$\begin{align*} I_{T C 1}=&\frac{1}{2} \mu_{n} C_{o x} \frac{W_{1}}{L_{1}}\\ &\times\left(V_{R S T_- 1}-V_{R S T_- 2}-V_{T H}-\Delta V_{T H_- R S T}\right)^{2}\\ &\times\left(1+\lambda V_{R S T_- 2}\right) \end{align*}$

(7)

$\begin{align*} I_{T C 2}=&\frac{1}{2} \mu_{n} C_{o x} \frac{W_{1}}{L_{1}}\\ &\times\left(V_{S I G_- 1}-V_{S I G_- 2}-V_{T H}-\Delta V_{T H_- S I G}\right)^{2}\\ &\times\left(1+\lambda V_{S I G_- 2}\right) \end{align*}$

(8)

In the same way, the relationship between the current and the voltage in the two output processes of $\mathrm{M}_{\mathrm{S}\mathrm{F}2\mathrm{A}}$ is

$\begin{align*} I_{T C A 1}=&\frac{1}{2} \mu_{n} C_{o x} \frac{W_{2}}{L_{2}}\\ &\times\left(V_{R S T_- O U T}-V_{R S T_- 2}-V_{T H}-\Delta V_{T H_- R S T}\right)^{2}\\ &\times\left(1+\lambda V_{R S T_- 2}\right) \end{align*}$

(9)

$\begin{align*} I_{T C A 2}=&\frac{1}{2} \mu_{n} C_{o x} \frac{W_{2}}{L_{2}}\\ &\times\left(V_{S I G_- O U T}-V_{S I G_- 2}-V_{T H}-\Delta V_{T H_- S I G}\right)^{2}\\ &\times\left(1+\lambda V_{S I G_- 2}\right) \end{align*}$

(10)

According to Eqs.(7)-(10), we can get

$\begin{equation*} V_{R S T_- O U T}-V_{S I G_- O U T}=V_{R S T_- 1}-V_{S I G_- 1} \end{equation*}$

(11)

From the above analysis, we can see that the non-linear problem in the output process of the traditional source follower is eliminated by the negative feedback self-establishment technology. At the same time, combining with the output range expansion technology proposed in section Ⅱ, the characteristics of the 8T global shutter pixel are brought to the extreme, which provides an excellent solution for the design of the low noise and high linear CMOS image sensor.

Ⅳ. Experimental Results and Discussion

The method proposed in this paper has been effectively verified in a 1024 × 1024 pixel scale CMOS image sensor chip based on 55nm 1P4M CMOS technology. The prototype verification chip is shown in Fig. 6. The technology proposed in this paper is verified in a sensor chip. The middle area is the pixel array, and the two sides of the array are the switching circuits of the sampling capacitor bottom plate. The lower part of the array is the layout of the column level readout circuit. In order to ensure the integrity of the signal, the linearization circuit is at the forefront of the output of the column line for sampling.

Figure 6. Prototype CMOS sensor chip

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When the swing of the FD point is 2V, the output voltage swing of the 8T pixel structure without the extension technology is only 0.95V after being outputted by a two-stage source follower. But the output swing can reach 2V after adopting the extension approach proposed in this paper, as shown in . It can be seen that the on-chip switch is consistent with the state of the sample hold and readout process, that is, the switch $\mathrm{S}_{3}$ is turned on in the sampling phase, the bottom plate of the sample hold capacitor is grounded, the switch $\mathrm{S}_{4}$ is turned on in the reading phase, the bottom plate of the sample hold capacitor is connected with $\mathrm{V}_{\mathrm{C}}$ potential, and there is a certain dead time in the design. Moreover, this method does not add extra pixel area and power consumption. Fig. 8 shows the verification results of the linearization. It can be seen that the voltage of the linearization output terminal almost coincides with the voltage curve of FD point by observing the output terminal of pixel source follower (lower curve in the figure) and the output terminal of linearization circuit (upper curve in the figure), . Because the latter stage needs a correlated double sampling processing, subtracting the two sampled signals, the difference between the FD point voltage and the two can be analyzed separately. During the variation of the FD point voltage from 1.3 to 3V, the linearized output varies accordingly, resulting in an error of only 0.3mV and the output error of the source follower is up to 280mV. It can be seen that this correction method optimizes the error introduced by nonlinearity of three orders of magnitude, and the power consumption introduced is only 23.1μw, accounting for less than 0.01% of the power consumption of the whole chip. Finally, Table 1 gives the characteristics summary of the image sensor test chip, and Fig. 9 shows the raw image taken by the prototype sensor chip.

Figure 7. Verification results of swing extension

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Figure 8. Verification results of linearization correction

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Table 1. Characteristics summary of image \\sensor test chip

Technology	$55 \mathrm{nm} 1 \mathrm{P} 4 \mathrm{M}$
Numbers of pixel	$1024 \times 1024$
Supply	$3.3\mathrm{V}/1.2\mathrm{V}$
Swing range	$2\mathrm{V}$
Full well capacity	$91 \mathrm{k}$
linearity	$99.98 \%$
Frame rate	60
Programed gain	$\times 1\sim\times 4$
ADC	$12~\mathrm{bit} / 14~\mathrm{bit} / 16~\mathrm{bit}$
Dynamic range(intrinsic)	$80\mathrm{dB}$
SNR	$49\mathrm{dB}$
Read noise	$7~\mathrm{e}^{\text{-}}$
Sensitivity	$5.6 \mathrm{V} / \mathrm{lux} \cdot \mathrm{s}$

| Show Table

DownLoad: CSV

Figure 9. Raw image taken by the prototype sensor

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Ⅴ. Conclusions

In this paper, aiming at the high-end global shutter CMOS image sensor which is in urgent need at present, the characteristics of the global shutter pixel are studied, focusing on the analysis of the limitation of swing of the 8T pixel structure and the origin of the output nonlinearity. Without sacrificing the filling factor, the method of the programmable voltage outside the array on the chip is used to improve the swing of the pixel, and the original reset and the image signal are restored by the negative feedback self-establishment technology. Finally, an actual CMOS image sensor chip with the scale of $1024 \times 1024$ pixels is used to verify the validity. The test results show that the output range is expanded from 0.95V to 2V, and the error introduced by nonlinearity is sharply reduced from 280mV to 0.3mV. Most importantly, the output range expansion circuit does not increase the additional pixel area and the power consumption. The power consumption of linearity correction circuit is only $23.1 \upmu \mathrm{W}$ , accounting for less than 0.01% of the whole chip power consumption. It can be seen that the method proposed in this paper improves the swing of 8T pixel unit by more than twice and the linearity by three orders of magnitude, which is a good help for the application of the high-end global shutter CMOS image sensor.

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6.	Al Tarabsheh, A., Alheeh, H. Design and Simulation of a 3-Transistor Active Pixel Sensor Using MATLAB Simulink. 2022. DOI:10.1109/ACIT57182.2022.9994188

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An Improved Global Shutter Pixel with Extended Output Range and Linearity of Compensation for CMOS Image Sensor