Volume 31 Issue 1
Jan.  2022
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WANG Tonghui, ZOU Jiaxuan, QI Huanhuan, WANG Xi, WANG Jingbo, ZHANG Hong. A Programmable Pre-emphasis Technique with Combined RLC Source Degeneration for High-Speed Serial Link Transmitters[J]. Chinese Journal of Electronics, 2022, 31(1): 52-58. doi: 10.1049/cje.2021.00.055
Citation: WANG Tonghui, ZOU Jiaxuan, QI Huanhuan, WANG Xi, WANG Jingbo, ZHANG Hong. A Programmable Pre-emphasis Technique with Combined RLC Source Degeneration for High-Speed Serial Link Transmitters[J]. Chinese Journal of Electronics, 2022, 31(1): 52-58. doi: 10.1049/cje.2021.00.055

A Programmable Pre-emphasis Technique with Combined RLC Source Degeneration for High-Speed Serial Link Transmitters

doi: 10.1049/cje.2021.00.055
Funds:  This work was supported by the National Natural Science Foundation of China (61974118, 62004156)
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  • Author Bio:

    received the B.S. degree in microelectronics science and engineering from Xi’an Jiaotong University (XJTU), Xi’an, China, in 2019. He is currently pursing the M.S. degree in electronic science and technology from Xi’an Jiaotong University. His research interests include analog interface and high-speed SerDes circuit design. (Email: wang578503930@stu.xjtu.edu.cn)

    received the B.S. degree in materials science and engineering from Huazhong University of Science and Technology, Wuhan, China, in 2005, and M.S. degree in communication and information systems from Guilin University of Electronic Technology, Guilin, China, in 2009. He is working toward the Ph.D. degree in microelectronics from Xidian University, Xi’an, China. Since 2009, he has been with China Electronic Technology Group Corporation, No.58 Research Institute, Wuxi, China, where he is involved in CMOS analog and mixed mode integrated circuit design, especially Clock and PLL

    received the B.S. degree in electronic science and technology and the M.S. degree in microelectronics and solid-state electronics from Xi’an Jiaotong University, Xi’an, China, in 2005 and 2008 respectively. From 2008 to 2018, she focused on high speed analog and mixed-signal CMOS circuits such as frequency synthesizers and data transceivers. Since 2018, she has been working as an Engineer in Xi’an Jiaotong University, where she is pursing the Ph.D. degree in microelectronics

    received the B.S. degree in microelectronics science and engineering from Xi’an Jiaotong University, Xi’an, China, in 2019. He is currently pursing the M.S. degree in electronic science and technology from Xi’an Jiaotong University, Xi’an, China. His research interests include analog interface and PLL circuit design

    received the B.S. degree in electronic information engineering from Northwest A&F University, Xianyang, China, in 2018. He is currently pursing the M.S. degree in integrated circuit engineering from Xi’an Jiaotong University, Xi’an, China. His research interests include analog interface and high-speed SerDes circuit design

    (corresponding author) received the B.S. degree in electronic engineering from the Xi’an University of Technology in 2000 and the Ph.D. degree in electronic engineering from XJTU, in 2008. Since 2008, he has been with the Department of Microelectronics, XJTU, where he is currently a Professor. From June 2009 to Sept. 2009, he was a Visiting Scholar at KU Leuven and IMEC, Belgium. From 2016 to 2017, he was a Visiting Professor with the Department of the Electrical and Computer Engineering, University of Toronto. His research interests include analog/mixed-signal IC design, such as ADC, low-power and low-voltage references, and bio-medical ICs. (Email: hongzhang@xjtu.edu.cn)

  • Received Date: 2021-02-02
  • Accepted Date: 2021-05-10
  • Available Online: 2021-10-08
  • Publish Date: 2022-01-05
  • This paper presents a clock-less programmable pre-emphasis technique realized by a driver with combined resistive-inductive-capacitive source degeneration for high-speed serial link transmitters. The addition of a series inductive-capacitive resonance network expands the bandwidth of the driver without lowering down the pre-emphasis gain. The driver with the proposed pre-emphasis technique provides adjustable gain from mid-frequency to high-frequency which is controlled by a tunable tail current, offering the capability for the transmitter to adapt to different cable loss from 0 to 6 dB. The driver has been employed in a 2:4 multiplexing and cable driving integrated circuit for 1.65 Gbps high-definition-multimedia-interface and digital-visual-interface application to drive up to 7 m 24-American-wire-gauge cable. Fabricated in 180 nm SiGe BiCMOS technology, the transmitter consumes 68.6 mW for 6 dB pre-emphasis under 3.3 V power supply.
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