CAO Huamin, WANG Qi, LIU Fei, et al., “A Novel Plane-Based Control Bus Design with Distributed Registers in 3D NAND Flash Memories,” Chinese Journal of Electronics, vol. 31, no. 4, pp. 647-651, 2022, doi: 10.1049/cje.2021.00.283
Citation:
CAO Huamin, WANG Qi, LIU Fei, et al., “A Novel Plane-Based Control Bus Design with Distributed Registers in 3D NAND Flash Memories,” Chinese Journal of Electronics, vol. 31, no. 4, pp. 647-651, 2022, doi: 10.1049/cje.2021.00.283
CAO Huamin, WANG Qi, LIU Fei, et al., “A Novel Plane-Based Control Bus Design with Distributed Registers in 3D NAND Flash Memories,” Chinese Journal of Electronics, vol. 31, no. 4, pp. 647-651, 2022, doi: 10.1049/cje.2021.00.283
Citation:
CAO Huamin, WANG Qi, LIU Fei, et al., “A Novel Plane-Based Control Bus Design with Distributed Registers in 3D NAND Flash Memories,” Chinese Journal of Electronics, vol. 31, no. 4, pp. 647-651, 2022, doi: 10.1049/cje.2021.00.283
(corresponding author) was born in 1987. She received the B.E. degree in integrated circuit engineering from Tsinghua University, China, in 2012. She is a Ph.D. candidate of Institute of Microelectronic, Chinese Academy of Sciences, and the University of Chinese Academy of Sciences. Her research interests include circuit design in memories and design for testability. (Email: caohuamin2005@163.com)
received the Ph.D. degree from Fudan University, China, in 2005. He is a Professor in the Institute of Microelectronic, Chinese Academy of Sciences, and the University of Chinese Academy of Sciences. His research interests include novel memory design, error correction code, and mass storage techniques. (Email: wangqi1@ime.ac.cn)
received the Ph.D. degree from Peking University, China, in 2003. He is a Professor in the Institute of Microelectronic, Chinese Academy of Sciences, and the University of Chinese Academy of Sciences. His research interests include novel memory design, phase lock loop, and analog digital converter. (Email: liufei@ime.ac.cn)
received the Ph.D. degree from Peking University, China, in 2003. He is a Professor in the Institute of Microelectronic, Chinese Academy of Sciences, and the University of Chinese Academy of Sciences. His research interests include process, device characterization, and reliability of novel flash memory device. (Email: huozongliang@ime.ac.cn)
This work presents a novel plane-based area-saving control bus design with distributed registers in 3D NAND flash memory. 99.47% control signal routing wires are reduced compared to the conventional control circuit design. Independent multi-plane read is compatible with the existing read operations thanks to the register addresses are reasonably assigned. Furthermore, power-saving register group address-based plane gating scheme is proposed which saves about 2.9 mW bus toggling power. A four-plane control bus design with 20K-bits registers has been demonstrated in field programmable gate array tester. The results show that the plane-based control bus design is beneficial to high-performance 3D NAND flash memory design.
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