A Novel Plane-Based Control Bus Design with Distributed Registers in 3D NAND Flash Memories

This work presents a novel plane-based area-saving control bus design with distributed registers in 3D NAND flash memory. 99.47% control signal routing wires are reduced compared to the conventional control circuit design. Independent multi-plane read is compatible with the existing read operations thanks to the register addresses are reasonably assigned. Furthermore, power-saving register group address-based plane gating scheme is proposed which saves about 2.9 mW bus toggling power. A four-plane control bus design with 20K-bits registers has been demonstrated in field programmable gate array tester. The results show that the plane-based control bus design is beneficial to high-performance 3D NAND flash memory design.