Volume 30 Issue 3
May  2021
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WU Tao and YANG Ailin, “A Simple BCH Decoder for NoC Interconnects and SoC Buses,” Chinese Journal of Electronics, vol. 30, no. 3, pp. 444-450, 2021, doi: 10.1049/cje.2021.03.007
Citation: WU Tao and YANG Ailin, “A Simple BCH Decoder for NoC Interconnects and SoC Buses,” Chinese Journal of Electronics, vol. 30, no. 3, pp. 444-450, 2021, doi: 10.1049/cje.2021.03.007

A Simple BCH Decoder for NoC Interconnects and SoC Buses

doi: 10.1049/cje.2021.03.007

This work is supported by the Fundamental Research Funds for the Committee of Science and Technology in Shenzhen (No.GJHZ20160229160351498).

  • Received Date: 2018-11-15
  • Network on a chip (NoC) uses packet-switched network to implement interconnections in System on chip (SoC). In SoC design, performance and energy efficiency are respectively the first and second priorities, and optimal on-chip communication should decrease the power consumption and area overhead. In this work, a simplified BCH codec is proposed for reliable communication in NoC and SoC. It performs BCH error corrections without Berlekamp’s algorithm, only using reduced syndrome bits to determine error patterns. The error locations can be found by looking up tables, by which the possible errors are directly corrected. Only one matrix product and one ROM access are required in the BCH decoder. The proposed (20, 8, 2) and (31, 16, 3) decoders in the paper can be easily applied for error corrections of interconnects and buses for NoC and SoC. It is also beneficial to correct data lines without length definition and control lines without storage.
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