Volume 30 Issue 3
May  2021
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WU Tao, YANG Ailin. A Simple BCH Decoder for NoC Interconnects and SoC Buses[J]. Chinese Journal of Electronics, 2021, 30(3): 444-450. doi: 10.1049/cje.2021.03.007
Citation: WU Tao, YANG Ailin. A Simple BCH Decoder for NoC Interconnects and SoC Buses[J]. Chinese Journal of Electronics, 2021, 30(3): 444-450. doi: 10.1049/cje.2021.03.007

A Simple BCH Decoder for NoC Interconnects and SoC Buses

doi: 10.1049/cje.2021.03.007
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This work is supported by the Fundamental Research Funds for the Committee of Science and Technology in Shenzhen (No.GJHZ20160229160351498).

  • Received Date: 2018-11-15
  • Network on a chip (NoC) uses packet-switched network to implement interconnections in System on chip (SoC). In SoC design, performance and energy efficiency are respectively the first and second priorities, and optimal on-chip communication should decrease the power consumption and area overhead. In this work, a simplified BCH codec is proposed for reliable communication in NoC and SoC. It performs BCH error corrections without Berlekamp’s algorithm, only using reduced syndrome bits to determine error patterns. The error locations can be found by looking up tables, by which the possible errors are directly corrected. Only one matrix product and one ROM access are required in the BCH decoder. The proposed (20, 8, 2) and (31, 16, 3) decoders in the paper can be easily applied for error corrections of interconnects and buses for NoC and SoC. It is also beneficial to correct data lines without length definition and control lines without storage.
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  • C. Grecu, A. Ivanov, P. Pande, et al., “An initiative towards open network-on-chip benchmarks”, in OCP-IP, 2007.
    B. Fu and P. Ampadu, Error Control for Network-on-Chip Links, New York, Dordrecht, Heidelberg, London: Springer, 2012.
    E. L. Prasad, M. N. G. Prasad and A. R. Reddy, “HSRDN: High-speed router design for various NoC topologies”, Chinese Journal of Electronics, Vol.29, No.2, pp.281–290, 2020.
    M. Vinodhini and N.S. Murty, “Hamming based multiple transient error correction code for NoC interconnect”, Lecture Notes in Electrical Engineering, Vol.711, 2021.
    C. Condo, M. Martina, and G. Masera, MP-SoC/NoC Architectures for Error Correction, ser. Advanced Hardware Design for Error Correcting Codes, C. Chavet and P. Coussy, Eds., Cham: Springer, 2015.
    J. Nurmi, H. Tenhunen, J. Isoaho, et al., Eds., Interconnect-Centric Design for Advanced SOC and NOC, Kluwer Academic Publishers, 2005.
    R. Elbaz, L. Torres, G. Sassatelli, et al., “A parallelized way to provide data encryption and integrity checking on a processor-memory bus”, 200643rd ACM/IEEE Design Automation Conference, pp.506–509, 2006.
    D. Kim, I. Yoo and I.-C. Park, “Fast low-complexity triple-error-correcting BCH decoding architecture”, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.65, No.6, pp.764–768, 2018.
    T. Wu and E. J. Yang, “A simplified BCH codec for network on a chip”, 29th Annual Conference of Circuits and Systems of Chinese Institute of Electronics, Changchun, pp.70–75, 2018.
    S. J. Lomonaco, “An example of the BCH code decoding algorithm”, https://www.csee.umbc.edu/lomonaco/f07/653/handouts/BCH-Code-Example.pdf, Lecture Notes, 2007.
    S. Lin and D. J. Costello, Error Control Coding: Fundamentals and Applications, New Jersey: Prentice Hall, 1983.
    J. Zhang, Z. Wang, Q. Hu, et al., “Optimized VLSI design of fast parallel BCH (2184, 2040) encoder”, Journal of Circuits and Systems, Vol.11, No.1, pp.88–94, 2006. (in Chinese)
    M. Finiasz, P. Gaborit, and N. Sendrier, “Improved fast syndrome based cryptographic hash functions”, eCRYPT Hash Workshop, 2007.
    J. Yeon, S.-J. Yang, C. Kim, et al., “Low-complexity triple-error-correcting parallel BCH decoder”, Journal of Semiconductor Technology and Science, Vol.13, No.5, DOI:10.5573/JSTS.2013.13.5.465, 2013.
    B. Sklar, “Reed-solomon codes”, Available at: http://ptgmedia.pearsoncmg.com/images/art_sklar7_reed-solomon/elementLinks/art_sklar7_reed-solomon.pdf, 2009-6-9
    D. V. Sarwate and N. R. Shanbhag, “High-speed architectures for Reed-Solomon decoders”, IEEE Transactions on VLSI Systems, Vol.9, No.5, pp.641–655, 2001.
    N. S. Naik and K. Gupta, “An efficient reconfigurable FIR digital filter using modified distribute arithmetic technique”, International Journal of Emerging Technology and Advanced Engineering, Vol.5, No.6, pp.152–156, 2015.
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